ISSUE WITH RESET SIGNAL PASSED TO CYPRESS CHIP FROM FPGA

[kalyansrinivas]

Hi all,
We had a VIRTEX-4 Fpga and a cypress controller(CY7C68013) on our board the reset signal for CYPRESS chip comes from FPGA(VIRTEX-4). The problem we are facing is that for some reason the reset coming from FPGA doesnt enable the cypress chip but when forced externally the chip takes it properly . Do i need to make any settings in XILINX ISE to make the IO driven from FPGA looklike a reset signal passed from external environment

Thankyou in advance

M Kalyansrinivas

 

[it_boy]

Could not understand you properly.
but, have you checked if the reset at the output of the FPGA is getting asserted? Have you checked with an oscilloscope?
How are you generating the reset in the FPGA? does it meet the minimum period required for CY7C68013?

 

[kalyansrinivas]

yes the reset at output of fpga is getting asserted properly i have checked in oscilloscope by probing the input to cypress reset pin

i am doubting wether to set it(reset) as PULLUP I/O to resemble the external reset and also any changes in map properties needed