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Recent content by isamel85

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    Describe in VHDL a generator parallel 4 bits to serial 1 bit

    This is my test bench: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_gen IS END test_gen; ARCHITECTURE behavior OF test_gen IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT generateur_bits PORT( Output_data : OUT std_logic...
  2. I

    Describe in VHDL a generator parallel 4 bits to serial 1 bit

    I tried it but it still gives me a single output state (either 0 or 1) even if I have a new rising edge, the value remains the same library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity generator_bits is port ( Output_data : out std_logic; Clock_250kHz : in...
  3. I

    Describe in VHDL a generator parallel 4 bits to serial 1 bit

    Hello, I want to describe in VHDL a generator parallel 4 bits to serial 1 bit. Indeed, at each clock edge (250 kHz), we take only one bit starting with the least significant bit (LSB). Example: Input = "0101" (over 4 bits) So at first clock edge, output = '1' (LSB) Second clock edge, output =...
  4. I

    INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate.

    Who has the same problem can give me a hand? thanks so much! the problem is: INTERNAL_ERROR:Xst:cmain.c:3464:1.56 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support. knowing that the Release version...
  5. I

    Digital to analog converter with FPGA

    Hello, Actually I am looking for a digital to analog converter (preferably an evaluation board) in order to connect an FPGA with a RF signal generator N9310A (he plays the role of an I and Q modulator and includes two inputs analog I and Q on rear panel and he can transpose the two analog...
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    [MOVED] Reading binary data over the serial port

    Re: Reading binary data over the serial port The last code missed the writing data; I put only the opening and closing of the port and the reception of the data; now you can check the entire code: s=serial('COM1'); % Create a serial port object %Configure property values...
  7. I

    [MOVED] Reading binary data over the serial port

    Hello In fact, I want to acquire a 8-bit binary data on serial port using Matlab (eg 00001100 in binary or 12 decimal). I make a test loop back just sending that data over the port and receive on the same port, knowing that sending code works fine and I checked it by HyperTerminal. I tried...
  8. I

    [SOLVED] RS-232 port and XUPV5 LX110T evaluation platform (Xilinx)

    Hello, In fact, I worked with XUPV5-LX110T evaluation platform (Xilinx). Indeed, I tried to send a data from Matlab script (communication protocol) on the RS-232 serial port, where: - I use the RS-232 Null Modem (DB9) Female-Female between the computer and the platform; - The data sent is 8...
  9. I

    FPGA from / to PC Data communication

    Hello, In fact, I'm working on a project which aims to implement a reconfigurable Zigbee tranceiver on XUPV5-LX110T Evaluation platform which integrates a Virtex 5 FPGA. I am currently in the phase of real test. First, I want to send my data from a PC to FPGA and receive it (to treat my...
  10. I

    FPGA from / to PC Data

    Hello, In fact, I'm working on a project which aims to implement a reconfigurable Zigbee tranceiver on XUPV5-LX110T Evaluation platform which integrates a Virtex 5 FPGA. I am currently in the phase of real test. First, I want to send my data from a PC to FPGA and receive it (to treat my...
  11. I

    Generating a signal (a VHDL description) with a well-defined frequency in a FPGA

    Hello, In fact, I'm working on a project that aims to put a communication platform to interact with hydrogen sensor wirelessly. The platform consists of an evaluation board from Xilinx ML505 (on which there is a Virtex 5) which will implement the baseband digital processing and another board...

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