Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by infosrig

  1. I

    Modelsim Optimization

    What does modelsim optimization mean. "voptflow =1" as default. by turning it off only signal waveforms apperaing. this can be found in modelsim.ini file.
  2. I

    Call TCL tasks inside Testbench ?

    nothing i found in abouve link., could u provide the proper link or doc..
  3. I

    how to learn the BUS architecture(PCI, PCI Express, AMBA...)

    Re: how to learn the BUS architecture(PCI, PCI Express, AMBA can u tell about BAR in PCI bus. pls say the Exact purpose of this.....
  4. I

    PCM data on PCI bus - is there PCM to PCI bridge?

    Re: PCM data on PCI bus Can u Explain about the Exact purpose of BAR in PCI? pls..
  5. I

    Gate count for implementing a PCI-X core in fpga?

    Hi, How you are implementing pci-x core, r u having IP CORE from xilinx? pls help.. iam also trying that to interface.. but the FPGA is not detecting in pc...
  6. I

    FPGA final year project for electronic engineering

    Re: fpga projects hi, iam trying to interface between PCI-x and FPGA LX330., the board is not detecting in the PC thru PCI-x but JTAG no probs. i tried in "lspci". pls help... expecting ur valuable suggestion..
  7. I

    LEFT shift operator for numbers

    Re: LEFT shift operator new operator <<< try it
  8. I

    The function of '>>>' and '<<<' operators in Verilog

    Re: verilog operator Thanks for ur valuable info...
  9. I

    what is the difference between these 2 verilog statements

    Re: what is the difference between these 2 verilog statement During execution "reg4" tekes the value at 0 time, then it wait for 10 time units to assign value to "reg3"., reg2 asusual nonblocking statement nothing difficult... hope help full....
  10. I

    i need pci initiator (master ) verilog code

    iam trying to interface pci-x with fpga v5 lx330 pls help
  11. I

    FPGA V5 LX330 with pci-x interface

    LX 330 is not detecting thru pci-x slot when iam connecting with PC. any driver is required... iam having IP core . pls help...

Part and Inventory Search

Back
Top