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What does modelsim optimization mean. "voptflow =1" as default. by turning it off only signal waveforms apperaing. this can be found in modelsim.ini file.
Hi,
How you are implementing pci-x core, r u having IP CORE from xilinx?
pls help.. iam also trying that to interface.. but the FPGA is not detecting in pc...
Re: fpga projects
hi,
iam trying to interface between PCI-x and FPGA LX330., the board is not detecting in the PC thru PCI-x but JTAG no probs. i tried in "lspci".
pls help...
expecting ur valuable suggestion..
Re: what is the difference between these 2 verilog statement
During execution "reg4" tekes the value at 0 time, then it wait for 10 time units to assign value to "reg3".,
reg2 asusual nonblocking statement nothing difficult...
hope help full....
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