Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
When I export CDL netlist from a schematic, the MOSFETs always have the model name P12/N12.
If I want to export MOSFETs netlist with model name like P/N, how to implement this?
In other words, if I want to create a reference schematic lib include the basic element, such as NMOS, PMOS, R...
About GVCO
I'm doing some design about GVCO and some problems are encountered.
My structure is based on inverters, two stage inverter and one NAND gate. The frequency is adjusted by voltage controled capacitor at the output of the inverter.There are two gvco, one works at the high gating data...
"However, there is probability (quite a little though) that the decoder won't identify such a situation and "fix" errors incorrectly (in fact, adding errors to the codeword)."
You mean this case could not be avoided?
It seems that there are few papers introduce the case that the number of errors is larger than the RS code error correction capability.
For RS(n,k), n-k=2t,
What result wolud be at the decoder output when the number of errors(En) larger than t.
When the En >t, I'm interest in the following...
veriloga loop filter
When constructing a pll with veriloga, I got the vco control voltage like in the attachment. It seems to be oscillating periodically.
Which block has problem according the vctrl waveform?
In behavior and transister level.
1. the lock range
2. the lock time
3. the pull in range
4. the pull in range
5. the pull out range
6. the hold range
7. the loop bandwidth
8. the close loop bandwidth
9. the phase noise
10. the jitter
11. the nature frequency
12. the damping factor
13. the vco...
I do AC analysis for the PLL,but an error result is gotten. I think the reason is that the pll system must be in lock state when AC analysis is done. But I don't know how to get this state( transistor level).
Sorry, I have no the linear model of CP.
I'm not familiar with PLL simulation for so...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
