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Re: P&R with only "LEF" file and NO "LIB&
Hi,
Yeah,with only "LEF" file you can do P&R.
Most of unmerged IP(esp. analog IP) provide LEF only for layout.
You must treat it as a blackbox when you're doing timing analysis and add port input delay or output delay manually.
BR,
iamchine
Hi,
You should define the port information in verilog code with input/output/inout only. You should post detail error info or your RTL code to get more answer.
BR,
iamchine
Re: How to P&R power/ground rings for a multi-voltage ch
hi flyankh,
I mean that digital part's voltage is different from analog IPs' voltage.Though for single voltage supply system,there're at least two rings for power/ground.Somebody told me power/ground rings must be laid on top metal,but I...
For minimum area,how to do it?
1) P&R rings on top-metal round by round?
2) P&R rings on samel round position metal by metal?
3) P&R on top-metal(horizontal) and the next lower(vertical) metal with vias connection to form rings round by round?
Which one is the best? Or any other better way...
Re: what's diffrent between SDF_anno and RC_annotated in sta
SDF files contain only delay data. If you do not provide any parasitic data,
PrimeTime uses wire load models for transition time calculation. If you want
to check post-layout DRC rules such as max_transition, you must provide valid...
Re: Why RTL version of IP core is more expensive, then Netli
I think the price from low to high as following : Hard Macro IP , Netlist Soft Macro IP, RTL Soft Macro IP.
Because the size and process can't be different from the Hard Macro IP.
Netlist IP's size can be changed to fit your need,but...
What's the relationship of min/max_delay,max_skew,frequency,rise/fall time with clock network's max_capacitance,max_transition?
I encountered a problem : STA's max_capacitance&max_transition violation(clock tree networks) is too big after layout.Can anyone help me?
The following is clock tree...
ncverilog encrypt
We want to encrypt our netlist after synthesis with DC.Our copartner should be able to simulate(VCS/NC-verilog) with the encrypted netlist.Which EDA tools /software you use?How do that?
Thank you !
otp quicklogic
If you are familiar with verilog and digital circuit design,it's not difficult.But it is OTP FPGA for its anti-fuse tech.This is the biggest difference with Altera&Xilinx's SRAM tech FPGA.
Re: Crypto on FPGA
What vale said is pretty well.
Normally,for RSA algo,1024bit/2048bit large integer modular exponent and modular multiplication co-process module implement is OK.
For prime field ECC,its co-process module architechture is similar with RSA,but is more quick and easier for its...
ISO7816 is the standard for contact smart card and ISO1443 is for contactless smart card.But they're not cryptographic standards.Normally,there're a 1024/2048 bit RSA co-process module and a DES/3DES module in the card which supports hardware encryption.You can refer to Infineon,ST,Philips and...
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