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I do have a sdc-File with following time constraints:
After running the TimeQuest I get following waveform output to one data input to the FPGA .
Question:
With which time constraint I can reduce the Data Delay time (4.316ns)? :?:
Thanks in advance
ok understood. In this case I use a clock of 125MHz.
If we consider this as fast IO, how would you determine the delay time(s) respectively how to constrain the IO's in such case?
Hello
I do have a ADC connected to an FPGA while the FPGA generates the ADC-Clock. This ADC-clock is the same as used insided the FPGA.
After running TimeQuest I see that for example the ADC_Clock and the ADC_OE outputs are unconstrained output ports of the FPGA.
Questions: :-|
- How do I...
Hello
I do have following signals:
pos : in std_logic_vector(15 downto 0) := (others => '0');
constant PtA : real := 1.0;
signal ang : sfixed(2*PtA_FP'high + 1 downto 2*PtA_FP'low);
Now I would like to multiply following expression with a type conversion to sfixed:
ang...
I would like to use the fixed point package from D. Bishop for an altera fpga. According to the header of the file
fixed_pkg_c.vhd it should be compiled into "ieee_proposed".
Could someone tell me how I can do that with Quartus?
thanks
I do have following block diagram which I would like to connect with a bus that use a generic parameter (adc). The blockdiagram looks like this:
The implementation for the file "block_name.vhd" is:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY block_name IS
--...
In QSYS I have an ADC, PLL and an Avalon-MM Read Master to access the internal ADC of the Altera Max10. The control and user interface of the Read Master are exported.
Now I struggle to setup the control interface to access the ADC channels. Mainly following signals...
Hello
I think I found the problem. I mismatched inputs with outputs. This means that MyMux has inputs while I was trying to connect those signals with the INPUT signal islv_adc_data.
Now I changed the PMOD_J4 and PMOD_J5 to bidirectional signals. Unfortunately I get this error message when...
When I connect "MyMux2" with a bus-line to the ADCdriver input (see picture) I get error messages like:
I share the same bus line coming from MyMux1 but here I do not get an error.
Does someone know how to solve this problem?
Thanks!
Following simple question:
When I add a SPI 3-wire serial interface in QSYS I can set several parameters like: Type, clock speed, data width etc..
So why do I need those parameters when I setup the SPI interface directly in VHDL? In other words, are those parameters only
valid when I this...
With Modelsim I would like to test a code but one signal always remains uninitialized. Here a code snipped to explain the problem with Modelsim:
-- Signal Declaration
signal shifter : std_logic_vector(0 to 6);
signal led_out_temp : std_logic;
process (reset_reset_n) is
begin
if...
Ok but how can I avoid it?
I simply would like to write a value to the output UserLed. As it is not possible (see first post) I introduced an internal signal but it is the same problem again.
Ok I see the problem. When I introduce a new signal led_int and change the code like this:
architecture bdf_type of Test is
signal led_int : STD_LOGIC_VECTOR(4 downto 0);
component misc
port (
reset_reset_n : IN STD_LOGIC...
I do have following VHDL code example:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Test IS
PORT
( Nios_Reset_n : IN STD_LOGIC;
UserLed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END Test;
ARCHITECTURE bdf_type OF Test IS
COMPONENT misc
PORT(...
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