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hi Klaus,
thanks for your kind reply. In another word, op-amp type comparators often have different rise and fall time, is that to say they have different driving capability for high&low outputs? If so, what's the reason behind it and why current mirror amplifier has equal driving capability...
how to understand the op-amp type comparator driving capability? it is said that current mirror amplifier, when used as a voltage comparator, has equal driving capability for both high and low outputs. what does it mean? what about other amp, i.e telescope amp?
can anyone explain it? thanks!
I need a medium threshold NMOS in my design,but there is no accessible 5V mvt NMOS in my process. So I have to use the 3V mvt NMOS. But in my design, its gate is connected to the 5V supply voltage. Will this be a problem? If does, how can I fix it. Any suggestion? Thanks!
hi jiripolivka, thanks for your reply! Actually the comparator requires an input common mode range beyond the supply rails. So both input terminal voltage may be greater than the supply rail. How can I make the design to meet such demands?
Are there any ways to realize such a operational amplifier type comparator with input range beyond the supply rail voltage,e.g, 4V input for 1.8V supply voltage? I only find some rail to rail implementations, but not beyond raii-to-rail. Can anyone give some suggestions and references. thanks a lot!
i come across a problem on the selection of common mode input voltage. The OTA (shown in fig1)is used to implement the SC S/H circuit in pipeline ADc and the subsequent MDACs. The supply voltage is 1.2V and the output common mode vlotage is supposed to be 0.6V. If I choose the Vcm,in also around...
your explanation is quite helpful and is an inspiration for me . thanks very much!
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Hi Dominik Przyborowski, I have read this document you recommended and it is really helpful. thanks very much for your so detailed information.
Could anyone give some explanations on the effect of load capacitance on the two-stage cascode compensated OTA design. What's the influence of Cload on the choice of compensation capacitor value and GBW , PM etc.? If Cload is too large or too small, what's the difference? thanks a lot!
in conventional pipeline ADC design, usually single-stage OTA is used whose noise contribution can be expressed directly associated with the sampling and feedback capacitors of each stage. In a two-stage OTA, because of miller or cascode compensation, OTA noise contribution is directly related...
Hi sarge,
Thanks for your helpful suggestion! I modified it and it works. the node of which I tested the noise voltage cannot be disturbed by noise since a constant ideal voltage is connected to it, right?
In a differential pair amplifier, the vid is supposed to be much smaller than Vov so as to maintain a good linearity. But what i confused about is that the amp is always used in a closed loop, in which case the vid can be rather small because of the large gain( two input terminals almost...
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