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Now I would like to run a post-layout simulation with sdf file back-annotated. The problem is that how I add the cell simulation verilog files of synthesis library into my final gate level netlist or verilog-xl simulator. There are more than 300 cell files, it's a very hard work to use include...
Now I am forwarding to post layout hold-time analysis from pre layout sta analysis. In my synthesis script I have set max delay for some pathes but no minimum delay. Now for hold-time should I set minimum delay for these pathes, if I need to set, how to determine the value?
First I would like to thank those ones who help me on the former topic STA problem. Now I have a new problem that from the timing report I found that there is a large transition time for a gate element in my gate level netlist. Because this is a pre-layout STA. So can anybody tell me that what...
Now I am tying to do pre-layout constrain for my project. The feature of this project is that only one 48MHz clock is available. After internal division it produces a 12MHz clock, all the output ports are synchronized to the 12MHz clock. Now I do a top level STA by putting all the inputs and...
Can anyone tell me how to set a cell or reference as a black box in synopsys DC enviroment. I have tried set_attribute cellname is_black_box true command, but it didn't work.
I have installed synopsys dc 2004 linux version on my RHEL AS3.0 OS. I modified my license file according to my hostname and my snpslmd path. Then I use lmgrd to start the license. But it reported "failure to open TCP port". So I try other TCP ports. However, it reported "TCP port already in...
rtl compiler hold time fixing
Hi, can anyone tell me how to estimate the setup and hold time for a given frequency during synthesis. How I account the setup and hold time listed in the synthesis library into my estimation.
When you design a part of a chip, do you receive the requirments of...
Hi, does anyone know that synopsys dc 2002, primetime 2002, formality 2002 linux version can be installed and run smoothly on RedHat Enterprise linux AS 3.0 or WS 4.0 platform? Thanks.
generated clock synthesis
I have a question when I did a multiple clock synthesis.
There is a source clock and I want to generate 4 differernt clocks(1/4 frequency of source clock) from this source clock like the definiton in the datasheet of microchip PIC16C84. Can I use these generated...
#delays in RTL
The correct way to achieve a exact delay is using counter. In your example you can use one couter, when the value reaches x it cause a event(R to R), when reaches y it cause another event(G to Y).
booth multiplier
Hi, every one, I have written a booth multiplier, But when I simulate it, I found that some times it can work well, some times it can't. I don't know what's wrong with my design. Please help me. Below is my code.
module...
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