How to set a cell or reference as a black box in synopsys DC enviroment?

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Can anyone tell me how to set a cell or reference as a black box in synopsys DC enviroment. I have tried set_attribute cellname is_black_box true command, but it didn't work.

 

[yrpavankumar]

black box synthesis

Setting a cell as a black box can be done in following way.
1. create a verilog file of the cell, which will be having only port declarations. (no functionality in it)
2. read this verilog file in DC environment.
3. set dont_touch attribute on this cell before compile.
This will create a netlist with the cell as a black box. Netlist simulation can be done using verilog behavioral mode for the same.STA can be done using timing model for the cell and during physical design we will be relacing it with physical info (may be LEF file).
Hope this answers your question.