STA problem with max-delay violation

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Now I am tying to do pre-layout constrain for my project. The feature of this project is that only one 48MHz clock is available. After internal division it produces a 12MHz clock, all the output ports are synchronized to the 12MHz clock. Now I do a top level STA by putting all the inputs and outputs constraints under 48Mhz clock. The problem is that there is a max-delay violation from one input to one output and the value of violation is very high to a level of exaggeration. Should I change the constraints by constraining all outputs to 12Mhz clock?

 

[satya_422]

Re: STA problem

Hi,
Just Give the constraints as a generated clock for the 12 Mhz clock..

It will check for voilations w.r.t. generated clock ..

--satya

 

[rameshsuthapalli]

STA problem

Hi all,

please define 12mhz clock as the generated clock from the 48mhz clock. and define all the input/output delay contrains according to the 12mhz clock for those inputs that r only depend on that clock.it may solve u r problem.

regards,
rameshs

 

[spauls]

Re: STA problem

Also provide realistic value of latency of generated clocks

 

[zhangpengyu]

STA problem

you should constraining all outputs to 12Mhz clock