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The point I am trying to make is: as long as there is DSP block, there should be a way to implement floating-point adder, but for some reason Xilinx didn't make it, and I wonder why.
Hello. I am now using floating-point IP generator in Xilinx ISE to generate double float adder. For Spartan-6, it only makes use of LUTs, while on 7 Series it is possible to utilize DSP48E1. Please explain to me, is there any fundamental difference between these DSP types that makes it...
next_tx_valid is being used in function update_rr, which is called from WAIT_ACK and WAIT_RESP states.
I re-ran map and fit a few times, and warning still appears, and next_tx_valid is still on the final netlist. And this is the only module.
Hmm, nope. I checked the post-fitting netlist, and it is still there. Maybe it has something to do with that next_tx_valid is used not directly in an always block, but within a function?
Hello. I am trying to synthesize a module written in SV and get this message despite I checked that signal is being used:
Warning: Verilog HDL or VHDL warning at crossbar.sv(28): object "next_tx_valid" assigned a value but never read
some code:
.......
logic next_tx_valid[SLAVES][1:3]...
Hello, I'm trying to implement source-synchronous output from Spartan-6. So I use a constraint to place output data registers into IOBs, and clock goes through ODDR2. So now clock and data switch almost simultaneously, but the downstream device requires a hold time of 1ns, how can I achieve...
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