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Help! Qu@rtus 30?
:?: 1: I setuped the Qu@rtus3.0 two mouth ago,which works ok.But last week, it awalys reports that it doesn't support the cyclone device and let me check the license! My notebook's OS is XP.
It is strange that the same Qu@rtus and the same way to generate the license one...
I have meet a company who can copy the PCB entirely! For the current FPGA that uses the PROM to configurate the FPGA,if you can read the data from PROM according the PROM timing requirement,you will design a equipment more easily.
Of course,this is copying equipement,not copying IP.
license maxplus2
The way of how to set the licentse.dat is diffirent between Xilinx and @ltera. Xlinx needs to add some word like SET LM_LICENSE_FILE="dIRECTION WHERE THE LICENSE.DAT" in autoexec.bat .But @ltera do not do like that.When Muxplus started,by toolsbar->help->license setup,then...
= period ts_clkin * 2
Why not use clk1 and clk2 as a enalbe controller signal and make the clk as system clock?
Thus ,the all chip can use only one clock:clk.
I meet a strange problem about synplicity for @ltera.
I use AC1K30 in my design and synplicity 7.23 for synthesis.Sometimes the synthesis may take few minutes,but the other time can not complete ,even hours!
When I change the chip from @ltera to Xilinx,example XC2S30,the synthesis speed will...
The jitter is more important for transmission, using 19M to get 2M will not meet the requirement of G.703 . using extern PLL to get 2M from 8k,which is may be divided from 19M, is the most popular solution .
The keywords "after" is used in RTL simulation only,and after synthesized,it will be abort.
If you want to realize delay in design,use counter will be good way and it will use some register. the more delay,the more need to be used!
I have just finished demo,the most difficult thing is programmable frequence generation,The PD can be finded at @ltera,it is good.but i have not find a good way to know whether the verifying freqence is the same of the reference
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