handsome
Junior Member level 3
derived clock synplify
hi all,in a design there are 3 clocks,which are clk ,clk1 and clk2. clk is the base clk and is expected to about 40Mhz,clk1 and clk2 are devided clks by clk. clk1 is devided by 2 and clk2 is devided by 4. how can i constrain these clks in synplify . should i constrain them in one group?if i do so,synplify will constrain my clk1 and clk2 with 40Mhz,this is not i want it to do. if i constrain them in the different groups,synplify will treat them as unrelated clks,but they are devided by the same base clk. how constrian them?and should i constrain them with multi_cycle constrains?
i do know how to do now!can you help me ??
thx
hi all,in a design there are 3 clocks,which are clk ,clk1 and clk2. clk is the base clk and is expected to about 40Mhz,clk1 and clk2 are devided clks by clk. clk1 is devided by 2 and clk2 is devided by 4. how can i constrain these clks in synplify . should i constrain them in one group?if i do so,synplify will constrain my clk1 and clk2 with 40Mhz,this is not i want it to do. if i constrain them in the different groups,synplify will treat them as unrelated clks,but they are devided by the same base clk. how constrian them?and should i constrain them with multi_cycle constrains?
i do know how to do now!can you help me ??
thx