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Recent content by hercules007

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    Looking for tutorials about TLM design

    Hi, Could somebody give me some toturials about transcation level modeling methodology? such as how to create transcators, or how to modeling HW models in transaction level. And what's the benefit for the system designers with TLM?
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    Is it possible to synthesize?

    I think it is FPGA flow! BTW, in ASIC design, the netlist after post P&R with physical tools can be resynthesized ? I have not done this operation before!
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    what is hot-topic in digital design now?

    Really? AMCC ceased ..... I am not the market analyzer, but I think if a new technology would be popular in the world, it must has a long way to go! We shouldn't only focus on their temporary market performance! C-port has stopped developing for a long time! At present, Intel 's IXP series is...
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    i am beginner,how to study analog circuit design?

    you can also study it with the help of some eda tools, such Hspice,etc. 
  5. H

    what is hot-topic in digital design now?

    Let me try to explain, NP is a software programmable chip! It has the independant instruction set and complicatied architecture! In general ,it has two ports , one to connect the network physical port, and the other is to connet switch fabric. It focuses on processing packets ,such as ...
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    Looking for a free 8051 IP core written in VerilogHDL

    Re: help: 8051IP core this IP core is wonderful !But is is written by VHDL! Here is a verilog IP core,and it is synthesisable! You can download it at: Added after 3 minutes: I have used it my design with Altera FPGA ! The mc8051 core can be synthsisable, but the ram ,rom and xram cound not...
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    Download: 8051 verilogHDL IPCORE!

    8051 verilog IP core! Include Verilog Source code , asm, testbench, userguide ,etc. This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation;
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    Looking for any information about SoC

    Re: SoC I think if we have done some practical works about SOC, and implemented with some IP cores in the projects, the paper will be more valuable than theory research ! In fact , SOC design is not easy than AISC design, although Design Reuse is very charming for the engineer...
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    Is there difference between VHDL by Modelsim and Active HDL?

    modelsim vhdl version support In the Modelsim se 5.8, it support vhdl 1076-2002! If the tools support the different version of IEEE vhdl standard, perhaps it will report errors in the compiler!
  10. H

    Which course should I choose DSP or VLSI ?

    DSP vs VLSI As an engineer, both of this two field have good future ! In fact , the application of DSP or IC chip, such as embedded system development is alos a good choice! It is mainly depending on your interest!
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    Need help on analog communication

    couch digital and analog communication systems Here is a book about your field: Digital and Analog Communication Systems (6th Edition) by Leon W. Couch I wish it will help you ! And you can also find more introduction about it here...
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    What is Rapid IO and Raceway in IO bus ?

    Re: RapidIO and Raceway thanks for your help, although I am not very clear about your project , I am doing some search on this field , and in the future ,I believe we will have chance to discuss some problems about it! Merry Chrismas!
  13. H

    What is Rapid IO and Raceway in IO bus ?

    RapidIO and Raceway Hi,guys What are these two new tech in IO bus? and are there some ebooks about these tech? thx!

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