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Recent content by hemal

  1. H

    Introduction to Place and Route Design in Vlsis By Patric Lee

    Hi, Do anyone have this book? Please forward it if you have. Thanks
  2. H

    Negative setup and hold multicycle paths

    Hi, can you be more specific? I know multicycle paths exist in case where the path delay is larger than single clock period. but that will be with positive multicycle override. My question is about negative multicycle paths. --Hemal
  3. H

    Is $readmemb synthesisable in Xilinx and Synopsys?

    Hi, You can store initial values of the rom in a text file. $readmemb function can be used to read it in 0 simulation time. refer samir palnitkar book for this. ---Hemal
  4. H

    Negative setup and hold multicycle paths

    Hi, Does anyone know if negative setup or hold multicycle paths exist in design? If yes then why? Regards, Hemal
  5. H

    Does anyone has the RTL code of ARM AHB-to-APB bridge?

    Hi, can anyone point me the link where i can find apb bridge rtl code? Thanks in advance, Hemal
  6. H

    verilog code for ARM APB bridge

    Re: ARM APB bridge Hi, can anyone point me the link where i can find apb bridge rtl code? Thanks in advance, Hemal
  7. H

    region of operation of mos transistor in CMOS circuits

    hi, can some one tell me in what region the mos transistors are operating in digital CMOS circuiits? cutoff & linear ??? or cutoff & saturation ??? --Hemal
  8. H

    berkeley ee240 video lectures

    ee240 berkeley video hi, i also want those lectures. pls upload it if you have got it. thanks in advance. hemal
  9. H

    The syntax for plotting eye diagram in Spice

    hi, can anyone tell me the syntax for plotting eye diagram in spice? i am using Tspice for simulation. thanks in advance, hemal kansara
  10. H

    analog lectures of UC berckeley

    analog lectures hi, does anyone know how to view / download the video lectures from UC berckeley? subjects ee240 ee140. they are on analog circuit design. what settings in my pc are required to watch them online. because i am not able to view it online also. i have flash plug-in and real...
  11. H

    Solution to the errors from Tanner/Tspice

    hi i changed the parameters as below. .options absi=5e-07 .options reli=0.01 .options numnd=3000 .options chargetol=1e-012 and now i am getting the desired output. i was trying to make a %N counter for the PLL. can you tell me how obove parameter effect when calculating the initial...
  12. H

    Solution to the errors from Tanner/Tspice

    hi even i am getting the same error. can anyone suggest the solution? thanks in advance.
  13. H

    help required in designing of phase detector and VCO for PLL

    nf phase detector hi, thanks for your response. I have designed the PLL and simulated it. Now i want to measure the phase noise. Here are my parameter values: Kvco = 287 MHz /V Kcp = 2*1 e-6/(2*pi) Wn = 6 * 1E6 Rp = 20K C1 = 5pF C2 = 0.1pF can u tell me how to measure the phase noise for...
  14. H

    help required in designing of phase detector and VCO for PLL

    phase frequency detector spice hi, i have tried 1st and 2nd order loop filter. But i am not getting the stable output at the loop fiter. There are variation of about 7-8mv which changes my stable frequency. what could be the reason for that? all the components individually working fine. but...
  15. H

    help required in designing of phase detector and VCO for PLL

    phase detector hi, can u suggest me the way to get the vco frequency range of 20% of its center frequency? i am using current sterved VCO given in the book by baker. thanks
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