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Recent content by helenpenghan

  1. H

    How to check 32bit spectre and 64 bit spectre

    I would like to check whether I am running at 32 bit spectre and 64 bit spectre. Could anyone tell me how to do so? And if I am running at 32 bit spectre, I wanna change it to 64 bit. How to do that also? Thank you. :smile:
  2. H

    How to build a fixed switching frequency hysteresis controller for buck converter?

    Hello, I am trying to build a hysteresis control for very high frequency DC-DC converter. However, one drawback of hystersis comparator is the variable switching frequency with different outputs. I need a fix switching frequency for the whole system to ensure certain bandwidth. Is there any...
  3. H

    How to design a frequency error detector and corrector circuit

    Hello, I am trying to design a frequency error detector and corrector for hysteresis comparator in DC-DC converter system. I would like to maintain the hysteresis comparator output running at reference frequency. What I need to compare the output clock signal from hysteresis comparator with a...
  4. H

    How to fix the floating gate errors in IBM assura checks?

    I added tiedown cells. it works and most of the errors are gone. Thanks
  5. H

    How to fix the floating gate errors in IBM assura checks?

    Antenna check errors in IBM. Need help! I am using IBM cmrf6sf 3 metal technology for the layout. When doing assura floating gate check for my complete circuit, there are lots of errors as: GR908, There are floating AM//ML/MA of pads. GR131: There are metal/(gate+15*tie-down)>200 areas at AM/ML...
  6. H

    bias circuit and differential buffer stage design

    Thanks. But what if I need several differential delay cells, the output is not rail-to-rail, will that affect the results? And do you have any idea how to size the symmetric loads? Thanks a lot.
  7. H

    bias circuit and differential buffer stage design

    Can anyone offer me any hints on the design of differential buffer stage and bias circuit? I have read the "Low-jitter process-independend DLL and PLL based on self-biased techniques", but I still get confused about some issues. Actually, I am trying to design a DLL for which can generate phase...
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