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As showing in the attachment, I need to generate a vdd rail regulated signal with a rtr input signal.
My question is how to change this circuit to get a nearly 50% duty cycle output signal.
Thanks in advance,
-Kevin
Thanks for your reply. I'm wondering if the attached figure is the structure you described.
If it is. How can I get the intended voltage?
Thanks in advance.
Thanks for reply. But it seems difficult that using a current starved inverter to meet my requirement. It relies on current and input capacitance, right?
BTW, delay is not what I am concerning about.
LVDS is actually somewhat like my design. But I am not quite familiar with that. Can you...
hi,
anyone got an idea to decrease the voltage of either rail of inverter output signal?
I need a 100mV~1.2V output signal and a 0V~1.12V output signal. Error within 10% @ 100mV and 1.12V.
can you help me with this design?
tinier, the better
Thanks in advance.
regards,
Kevin
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