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In the linear region a rds can be descript by rds = 1/(mu Cox W/L (VGS-VTH)). In a mos-cap VDS is equal to zero but what's the value for rds when VGS<VTH oder VGS<0?
What do you mean with "commutation"?
Structure (a) is in well to but can be used as a floating capacitor, too. (why? )
Is structure (c) less suited to be used as floating capacitor because of its p-well (and the resulting capacitance to the substrate) -- how does this additional capacitance...
Why can structure (d) be used as a floating capacitor but c not? An why only when it's on strong inversion mode? What property allows a gate mos-capacitor to be used as a floating cap?
I read in different boards that beff represents µeff*Cox*W/L but I coudn't find it in the documentary (except b0) could you give me a hint where I can find the definition of beff (in an more official document)?
I'm trying to find out the mobility of an nmos-transistor and captured the cadence operation point parameters -- where can i find the meaning of them?
(I already had a look at the bsim4 and cadence docs but unfortunately I couldn't find the meaning of beff and u, are some cadence documents that...
I tried to plot the capacitance as calculated with a bsim-model and I know that the spice software calculates the values like Cij = dQi/dVj but I don't know how that works. Esp. because Cdb and Cbd are different.
Could someone explain to me why Cdb and Cbd (resp Csb and Cbs) are different in my...
Re: Calaculation the capacitence of an mosfet c(VGS)
My objective is to see how the transistor behaves as an (gate-)capacitor and in the literature there are a lot of depictions that show the different modes of the fet a la accumulation, depletion and inversion. Therefore I tried to calculate...
Calaculation the capacitence of an mosfet c(VGS)
I tried to calculate the capacitance of simulated MOSFET (a la C = I / dV/dt) with an connected drain/source contact but why is there a different between the gate current and the current at the current-source? Is the current-source drawing a...
My aim is to make an image out of an schematic in cadence virtuoso without all of the displayed properties, ie I'd like to have only wires and compoents on the image. Is there away to hide all properties and than to show them again without disabling the properties manually for each component?
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