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Ideally It doesn't matter whether you are jogging Antenna affected Metal layer to Top or Bottom Metal Layer, Ultimately total area of that Metal layer which affected should be less than Area which causes Violation.
If you jog to upper metal layer area drastically decreases(only which is going...
Hi Thank you Subhash.
Since the core logic where i was facing this violation was almost had only fillers cells we removed it completely (its small region though).
Now im facing other LUP violation.
LUP.4 and LUP.5.0:1.5V__1.8V and LUP.5.6.0:1.5V__1.8V.
These violations are coming inside...
Hello friends,
I wann make sure what type of cells needs to be included and which needs to excluded while dumping verilog from EDI for LVS run.
Mainly my confusion is regarding ENDCAP ENDCAPTIE TBCAP TBCAPNW* CNRCAP* FILLTIE FILLTIEPW etc.
Because i dont find cdl (spice) of all these...
Hi Hkrist,
You need to take care DRC's during routing, but you cant make it zero.
So Use proper methodologies for routing, like spreading nets and avoiding routing congestion. spreading std cells etc
then tool will take care DRC's. Then in the end you can clean up DRC's manually based...
Hi Hkrist,
You can add it all over the region,
I think your memories meeting required metal density already(Generally memories/IP will be closed with DRC/LVS so internally they will take care of density as well)
And i think they ll have blockages as well.
So you dont need to worry about...
Hi Dgnani,
I'm facing this problem at top level, i would like to know how to add these gaurd rings.
My I/O is separated by Core logic at top level, but as for this violation, Core is within 60um from IP OD injector.
So i face this violation at core logic.
I would like to know how to add...
Hi Bsrin,
Thank you very much for your reply. Ya i think we are ok with this.
My confusion was TCD fill Vs TCD cell.. What i understood is
TSMC recommends to use DTCD cells based on area its 2mm X 2mm in 16nm.
But it also says if we cant keep these cells we can skip but need to maintain...
Hi Friends,
Is there any one working or have experience in 16FF TSMC process. Im working and in tapeout stage.
Need some help on some issues.
Please be in contact or add me as friend. I may seek your help.
1. My present issue is plz let me know is it mandatory to use DTCD cells 2X2mm...
Hey Erikl and Dharmaslice,
thanks both of them for the reply. I resolved it. Problem was it was comparing wrt 4th significant digit. You can look in to the error image i have attached.
the digits in source and layout are 3 and 4 respectively.
So i enabled HIGH_RESOLUTION...
Hi Friends,
Im running calibre for my LVS 28nm digital design, Im getting property errors with mismatch in gate length and with with max 1.56% and .06% difference respectively in layout vs schematic.
Can any one help me to resolve this? im confused about what value and where to set in rule...
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