16FF TSMC process help for TapeOut

[guruprasadds]

Hi Friends,
Is there any one working or have experience in 16FF TSMC process. Im working and in tapeout stage.
Need some help on some issues.
Please be in contact or add me as friend. I may seek your help.
1. My present issue is plz let me know is it mandatory to use DTCD cells 2X2mm?
TSMC recommends it or else it says skip it but maintain TCD layer density.
This is really confusing.
Please any one have any idea on this. Explain me.

 

[bsrin]

Hi GuruPrasad,
I think you need to maintain this density. If the chip size is larger than 1mmX1mm then foundry needs this density. Better to maintain or reserve the space for TCD fill. I have this kind of experience in every technology (40lp etc) where chip size is more than 1mmx1mm. But I haven't did in 16FF.

cheers,
bsrin.

 

[guruprasadds]

Hi GuruPrasad,
I think you need to maintain this density. If the chip size is larger than 1mmX1mm then foundry needs this density. Better to maintain or reserve the space for TCD fill. I have this kind of experience in every technology (40lp etc) where chip size is more than 1mmx1mm. But I haven't did in 16FF.

cheers,
bsrin.

Hi Bsrin,
Thank you very much for your reply. Ya i think we are ok with this.
My confusion was TCD fill Vs TCD cell.. What i understood is
TSMC recommends to use DTCD cells based on area its 2mm X 2mm in 16nm.
But it also says if we cant keep these cells we can skip but need to maintain TCD fill density.
So i though TCD Cell is same as TCD fill.
But looks both are different.

Hey I have one more problem, I appreciate your help.

I have LUP violation near I/O region. (LUP.2)
Its asking for N+ and P+ gaurd ring. I dint understand what needs to be done to create this gaurd ring.

LUP.2 : Within 15 um (<= 15 um) space from the OD injector, a P+ guard-ring (P+ pick-up ring) is required to surround a NMOS or a NMOS cluster. And a N+ guard-ring (N+ pick-up ring) is required to surround a PMOS or a PMOS cluster. (Figure XXX) Rule exclusion: LUP.2 doesn't apply to NMOS in DNW if both of the following conditions are true: 1. NMOS is inside DNW with voltage (Va) >= PMOS NW voltage (Vb) 2. NMOS DNW doesn't physically interact with PMOS NW
BESIDE_POST_DRIVER_NMOS NOT INSIDE PTAP_guard_ring_hole
BESIDE_POST_DRIVER_PMOS NOT INSIDE NTAP_guard_ring_hole

Thanks

 

[waydeer]

Hi GuruPrasad,
Based on tsmc's recommendation, there should be at least one FEOL Dummy TCD and one of respective BEOL Dummy TCD in each 2mmX2mm window. If there is not enough space to insert one Dummy TCD each 2mmX2mm due to pattern layout, you may skip it. But density of FEOL and Metal Dummy TCD should reach 50% and VIA dummy TCD should reach 30%. That mean that you need insert TCD in at least 50% area of your the whole die.

Thanks,
Wade