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Recent content by Guru59

  1. G

    zero cycle path in FPGA

    hello all, In one my ASIC designs we have a zero cycle path. How do we make sure this in FPGA prototyping. thanks
  2. G

    [need] NAND Write & Erase..why Erase of PAGE not possible..why BLOCK Erase

    Hi. Can anyone explain why ERASE of whole BLOCK is performed but WRITE can be performed to PAGE. Why ERASE of PAGE is not possible ? Is there any Physics behind this phenomenon. thanks
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    Xilinx LUT4 equivalent in Altera...how to program delays

    Thanks for the suggestion. Can you let us know what is good practice in such cases when the design is using LUT4 or so on ?
  4. G

    Xilinx LUT4 equivalent in Altera...how to program delays

    HI, I am required to change my design in Xilinx to Altera. Xilinx design uses LUT4_L delays in it sdesign. what is the equivalent Altera element ? Thanks
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    Fanout load of input pin in DC ....please explain

    anyone...please...
  6. G

    Fanout load of input pin in DC ....please explain

    Design Compiler calculates the fanout of a driving pin by adding the fanout_load values of all inputs driven by that pin. what is fanout_load of input pin and how is it calculated. thanks
  7. G

    interview qstn on comb ckt to remove less time pulse

    well i said combinational circuit... how can counter be a combinational.....?
  8. G

    interview qstn on comb ckt to remove less time pulse

    No...the interviewers were keen to know a synthesizable combinatinal DUT
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    interview qstn on comb ckt to remove less time pulse

    hello all,i faced an interview yesterday and was stuck with one particular question of digital design. the question is as design a Combinational logic which takes a train of pulses with different pulse width (1ns - 5ns) and produces pulses of only 5ns as output.it should discard pulse widths...
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    Can Multicycle path be solved using pipelining...?

    hi all, For eg : a path between two flops (FF1 - FF2) has a big comb. logic which gives my required output at 3 capturing clock of FF2. since there exists a multicycle path between two flops if i break my comb logic and use pipelining of same two regs ....is this a correct method ? Eg : FF1 -...
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    posedge & negedge flipflops using mux....correct me if w

    Hi all, Below is the verilog code for posedge and negedge flipflops using mux. I have also attached the pictorial representation of the circuit. Verilog code : module mux_ff( clk, in, out_pos, out_neg ); input clk; input in; output out_pos; output...
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    altera_mf.v in altera suite what is required in xilinx ?

    hello all, i have generated a RAM file in xilinx using core generator. now to simulate the RAM file or to use it in my blocks what files are required to be compiled. i mean to ask as altera_mf.v in altera suite what is required in xilinx.
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    Is default required for fully covered CASE statement

    hello all, is default case required for a fully covered CASE statement in verilog eg : case(state) 2'd00 : y<=a; 2'd01 : y<=b; 2'd10 : y<=c; 2'd11 : y<=d; endcase thanks
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    what is present in InterframeGap in ethernet

    Hello all, i know the duration of interframegap in ethernet is 96bits times but what is present in interframegap. is it 'z' or all ones ? "On reception, some interframe gaps may be smaller due to variable network delays, clock tolerances, and the presence of repeaters." what makes the above...
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    Can STA be done using Design Compiler ?

    hi everybody, we have design compiler but we do not have primetime.i have gone through Himanshu Bhatnagar book and it has scripts for DC as well primetime. can i apply the same scripts in DC for STA. for time being is it possible to run STA for our design using DC. thanks
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