Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Xilinx LUT4 equivalent in Altera...how to program delays

Status
Not open for further replies.

Guru59

Full Member level 4
Joined
Jul 10, 2006
Messages
217
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Activity points
2,812
HI,
I am required to change my design in Xilinx to Altera.
Xilinx design uses LUT4_L delays in it sdesign.
what is the equivalent Altera element ?

Thanks
 

there is the LCELL, but afaik, it is only usable for older (very old) devices.

Using LCELLS, or LUT4 is very very very bad design practice.
 

Thanks for the suggestion.
Can you let us know what is good practice in such cases when the design is using LUT4 or so on ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top