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The switch does what it says...
Some soft connection errors can be ignored if you understand why they are happening!
If you say which types of resistors are you using and post some picture from the resistor with the error signaling active it will be nice to try and have someone help you ;)...
No.
NMOS bulks are usually connected to GND because their well is shared across all your design.
Think of your NMOS well as the "black" layer you have in your layout editing tool.
So, if you have an NMOS connected to GND you cannot have another connected to a different potential!
If you need to...
Yes, if you want such a low dropout it will cost you quite big layout area (bigger W/L).
Nevertheless, I think you do not need to have such a high value for L.
So, if you reduce your L value, in order to maintain the same W/L relation (to have the low VDS drop that you want) you lower you W...
If you need something like say 6mm of Wtotal, name your PMOS instance like NAME<59:0> with the maximum W that the technology permits (100um).
That will give you the 6mm, because you end up in your netlist with 60 PMOS devices of W=100u and L=1u.
I do not Know what technology you are using, but...
I do not know that GPDK from cadence...
However, some technologies do not allow certain W and L configurations...simple as that.
Despite the node being "X"nm, that does not mean that every type of MOS in the technology can be as low as "X".
Sometimes it just has to be bigger than that.
Look at...
Did you tried to activate the LVS switch that enables the "smash" of serial resistors into 1 device?
If you have one device in you schematic, you should "force it".
Has dick_freebird said in the previous post, it is best to represent the schematic as similar as possible to the layout.
If you do...
If Cadence does not kindly provide the Calibre deck files (which makes sense since Assura is the Calibre competing tool), then it is not possible.
Unless someone had the "patience" to do the decks himself :shock:
It would not shock me if prices were different for different Universities...
EDAs do that with companies, they might also do it with Universities.
Regarding the PDKs...
Choose one that suits your needs however, if you have to choose between two, check their foundry production prices since it...
Didn't know that.
Thanks!
However, since at least Europractice is a program co-funded by EU to boost semiconductor knowledge in Europe, I hope it is cheaper XD
Yes, the PDKs are foundry specif process models and are not (from what I know) provided by the EDA vendors.
I know that Cadence has a generic PDK for their tools.
However, you cannot produce any prototypes with it since its for simulation/learning purposes only.
Since Cadence has a generic PDK...
Your are welcome!
Later on, if want to produce any Si you can then use Europractice and their MPW program despite being in Iraq.
If making prototypes is not a goal for a near future and you go for Cadence tools, you can get theirs GPDK and tackle any foundry licensing this way .
Good Luck ;)
Ok, I thought you were in Europe due to your profile location...
Nevertheless, you can contact the Cadence Academic Network and try and reach an agreement with them.
Probably other vendors should have similar programs too...
As for my personal opinion, I can only talk a little bit about the...
Don't you have the technology documents to find out how much is the resistance per square of each metal?
It will really depend on how long and wide your metal routing is throughout the different levels!
In my opinion, obtaining an estimation from Ron is far from accurate...
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