cannot match terminal counts for nmos4/pmos4

[WoAiHua]

my layout passed diva_DRC check but failed extracted. The error msg is
4 cannot match terminal counts for nmos4
2 cannot match terminal counts for pmos4
6 total errors found

Any idea?

 

[erikl]

Bulk contacts missing, or not correctly connected?

 

[WoAiHua]

Hi, Erikl: Thanks for the reply. My layout is post on this link.

https://www.edaboard.com/threads/291921/#post1248112

 

[erikl]

See my answer over there:

https://www.edaboard.com/threads/291921/#post1248112

 

[WoAiHua]

I think "cannot match terminal counts error" is caused by dummy cell as there are 4 NMOS dummies and 2 PMOS dummies in the layout.

the output 8 PMOS, the input 16 NMOS and current source 8 NMOS, that are using the same bulk/source, seem fine.

 

[erikl]

I think "cannot match terminal counts error" is caused by dummy cell as there are 4 NMOS dummies and 2 PMOS dummies in the layout.

Possibly. Also the dummies have to match, of course.

... the input 16 NMOS and current source 8 NMOS, that are using the same bulk/source, seem fine.

No: The input transistors and the current source cannot use the same bulk, as you have designed your schematic. If you want them (or probably need to) share the same bulk, you must not connect the bulk taps of the input transistors to their sources but to GND (VSS), like the current source transistor's bulk tap.

 

[WoAiHua]

After removing the dummy cells, the error "cannot match terminal counts for nmos4/pmos4" is gone. Now I need to figure out how to implement dummies.

Regarding NMOS bulk, it can be connecting to either S or gnd. Right? I read somewhere a while ago that it is best to always connect it to gnd. Is it true case?

 

[GriffelKin]

After removing the dummy cells, the error "cannot match terminal counts for nmos4/pmos4" is gone. Now I need to figure out how to implement dummies.

Regarding NMOS bulk, it can be connecting to either S or gnd. Right? I read somewhere a while ago that it is best to always connect it to gnd. Is it true case?

No.
NMOS bulks are usually connected to GND because their well is shared across all your design.
Think of your NMOS well as the "black" layer you have in your layout editing tool.
So, if you have an NMOS connected to GND you cannot have another connected to a different potential!
If you need to have your NMOS bulks connected to different potentials, you will need an additional mask to create a Deep-Nwell.
With this new layout mask, you created a new well (similar to what happens with PMOS devices) which is isolated from the global (substract) well (the "black" layer).

Try and read some documentation about the technology your are using.
Sometimes there are pictures there that show you the placement of each layer in 3D, which helps you get the idea of where "each layer goes"