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Recent content by googlegzh

  1. G

    RAM or registers for having 16*8 bit memory

    Re: ram or registers? I tell you should use FF ,because it safe
  2. G

    What are the disadvantages of CMOS?

    Re: CMOS ??????? hi ,now CMOS have many fualts ,but woe must do
  3. G

    how to use virtual clock inDC

    virtual clock sdc 3X
  4. G

    how to write tristate gate in verilog ,

    verilog tristate with active low it may "DC"
  5. G

    Datapath Logic Cell Design

    you may read verilog aout book
  6. G

    How to develop a 16-keypad encoder using VHDL?

    Verilog HDL your design is what?? u canont tell clear
  7. G

    Looking for books about cache memory or memory design

    cache design i too need some sram controll ebook
  8. G

    cadence tool ( -access +rwc bug )

    you should set -access +rwc ,or you can not run NC
  9. G

    who can explain this question for me?

    in alway ,it is a good habit to use "<="
  10. G

    VCS, NC-Verilog and Modelsim, which is the best simulator??

    i use NC_verilog ,but modelsim too good for VHDL and verilog mixture
  11. G

    How to find the gate count

    you may in DC command,it tell you gates
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