how to write tristate gate in verilog ,

[googlegzh]

verilog tristate with active low

it may "DC"

 

[eda_wiz]

assign TRI_OUT =(EN)? 1'bZ : ABC;

 

[rakko]

I think you got your equation backward. The assignment is actually the other way around.

 

[eda_wiz]

I think you got your equation backward. The assignment is actually the other way around.

well I guess it depends on whether the EN pin is active low or active high.

 

[soccer]

it is easy
assign tri_out =(enale)? 1'bZ : tri_in;

 

[AlexWan]

Usually, we use the tri-state pads in the pins of chip.

 

[billjoy]

inside a chip
we dont use tri state
(maybe for FPGA is OK, but ASIC normally not)
In ASIC
only PAD use tri-state
so you should only use tri-state (gate) in behavior code
not RTL code