Datapath Logic Cell Design

[Tartakovsky]

I'm trying to learn about datapath logic cells and design them using Verilog HDL and compare their performance. Does anyone know about any resources where i can research?

 

[googlegzh]

you may read verilog aout book

 

[quake]

design it or just simulated? if design, better use custom circuit design instead of
using Verilog. And you have to do layout yourself, and evaluating the performance
is critical.

 

[amarnath]

depending on the type of your application ,you may do a full custom design of the datapath.this will actually depend on the system requirements(area,speed etc).

regards
amarnath

 

[Tartakovsky]

Gotta simulate and compare performance as well. Right now i just need to get started somewhere. Learn in-depth about various kinds of cells, how they 'theoratically' compare with each other etc.

 

[soccer]

if you want compare the performance by simulation, you'd better use stucture model rather than rtl behavior model. gate level model is better choice for performance comparision.

 

[jackson_peng]

i convenient way is to elabrate the cell (adder, multiplier) in your synthesis tool libaray.
you can get a detail charactistic of each structure.