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I am testing a PLL which I designed with VCO oscillates at around 400MHz.
I find the lock on time is much slow than that what I simulated from around 150us to several seconds,
and what's more, after the PLL lock to a desired frequency 400MHz, it will stay there for around 10 seconds, and move...
I modified an old design which operates at much lower frequency, vco freq. 16MHz; I think I overlook this design paramter.
Do you have any literature for designing phase detector for higher frequency? thanks in advance
Hi, all,
I have a problem of having a strange frequency vs time curves as the image (Cadence simulation with real device). It seems there are steps in between and make the locking time much longer.
Could anyone tell me what is the problem? is it due to the dead zone for the phase detector or...
scale error adc
Hi All,
I have made a 10bit SA type ADC but it has very big
full scale error 6LSB. How can I improve it ? could
some1 give a help hands :o
Thx
What is the basic requirement of equipment for measuring a 14-bit resolution of a sigma-delta ADC, in particular to measure the Signal
to Noise ratio ?
I would like to check for the signal-to-noise ratio of a 14-bit ADC, so I am thinking a 16-bit sinewave source will be good for the purpose. I will also need to check for IM distortion with 2 sine wave sources.
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