What non-idealities will affect the SA type ADC accuracy?

[golohoyeah]

Accuracy of SA ADC

Could someone list what non-idealities will affect the SA type
ADC accuracy in term of design and layout issues ?

Thx

 

[uladz55]

Re: Accuracy of SA ADC

The main sources of a non-ideality for SA ADC are an offset voltage of comparator, a non-ideality of the elements, which make up the DAC (mismatching of capacitors or (and) resistors, non-ideality of switches).

To reject the noise from substrate and power supply use the fully differential architecture.

Typicaly SA ADC are suitable up to 12 bit resolution.
Using self-calibrating technique it's posible to achieve more than 16 bit resolution.

See in more detail in
R. Gregorian, Introduction to CMOS Op-amps and comparators.
Crystal Data Acquisition Products. Applications Reference Guide.

 

[piao]

Accuracy of SA ADC

You can using the offset cancellation technology to minimized the offset voltage of comparator. Then I think the Place & route are very important to your design. you can reference in RAZavi, Principles of Data conversion system design.

 

[StevenL]

Re: Accuracy of SA ADC

Also S&H settling issues become very important at higher speeds with a higher number of bits.

 

[yyliang]

Re: Accuracy of SA ADC

Hi, piao,do you have the book--- Principles of Data conversion system design? if you have the ebook, can you give me a share?Thank you.

 

[icfb]

Re: Accuracy of SA ADC

hi,uladz55
Do you have the ebook "R. Gregorian, Introduction to CMOS Op-amps and comparators"

thank you!

The main sources of a non-ideality for SA ADC are an offset voltage of comparator, a non-ideality of the elements, which make up the DAC (mismatching of capacitors or (and) resistors, non-ideality of switches).

To reject the noise from substrate and power supply use the fully differential architecture.

Typicaly SA ADC are suitable up to 12 bit resolution.
Using self-calibrating technique it's posible to achieve more than 16 bit resolution.

See in more detail in
R. Gregorian, Introduction to CMOS Op-amps and comparators.
Crystal Data Acquisition Products. Applications Reference Guide.

 

[JPR]

Re: Accuracy of SA ADC

Another source of inaccuracy in a high resolution SA ADC (using a cap DAC) would be switch feedthru. To make a high resolution, even with a split-DAC, MANY unit capacitors would be needed. In order to fit into a reasonable silocon area, each unit capacitor would be very small. This not only leads to matching errors, but also will tend to make switch feedthru more pronounced. Physically small switches help, but there is a limit before the switch resistance becomes too high. A fully differential design should help cancel switch feedthru effects, but since voltages would not be equal, the amount of charge injected would still not be equal.

 

[CDRCDR]

Re: Accuracy of SA ADC

capacitor matching will be a big issue if you use capacitor array