Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
don't trigger each time btn is a logic '1', instead trigger off an edge
always @(btn, btn_prev)
btn_re = btn & ~btn_prev;
always @(posedge clk)
btn_prev <= btn;
if (btn_re) begin...
your types and signal declarations should be between the architecture statement and begin
architecture behavior ...
signal xxxx...
begin
also, you don't want to assign array_name to coutner, you want to assign it to out7seg in your 2nd if
try initializing your array in the signal assignment...
in a lot of cases you can have something like this:
fpga output -> series resistor -> output driver ic -> series resistor -> receiver ic -> series resistor -> device, or whatever termination you want
you let the driver/receiver chips do all the heavy lifting and define the signaling standard...
what happened to incrementing the counter? the line: counter <= counter + 1; tricky posted.
also, in cases like this you may want to look at a case statement. will make the code a bit easier to read.
oh, you're assigning your output in two places. you don't need to assign your array to counter.
power dissipation at DC is one
in space applications series source termination is generally preferred to save on power consumption, compared to say parallel termination
thanks tricky.
ya, it turns out the component declarations were sitting inside a package in the 'library' file i was trying to use. needed to tack on an extra name in the use line and take off the entity.axcelerator in the instantiation.
kevin,
i think what was confusing me is it was getting...
well, i guess i left out a key piece of information.
my situation is different because we have special scripts and linked libraries depending on the fpga we're developing for. the problem is that the axcelerator library is not in my local directory with all the other files, but rather sitting...
modelsim doesn't complain when i instantiate the clock buffer like this:
library axcelerator;
use axcelerator.hclkbuf;
---
inst_hclkbuf : entity axcelerator.hclkbuf
port map (
pad => clk_in,
y => clk_out
);
when i go to synthesis using synplify, it errors out with the...
ah, you're right, i just noticed he mentioned the data width was only 8.
ya, good point about the dsps. i believe the coregen multiply blocks will default to using a dsp slice unless you specifically tell it not to, or it's at least an option.
it sounds like you're already doing the subtraction on one clock, and the multiplication on a subsequent clock once dif_enable is asserted. thats as good as you're going to get if you don't hand instantiate a math block or create one yourself.
an easy way to do it is if you use something like...
Re: design Engineer Role
lol
even when running at slower speeds, say 33 MHz, your rise times are still in the 1 ns range. you must take into consideration hundreds of different variables when routing signals, designing the board stackup, termination resistors, capacitive loading, and signal...
https://en.wikipedia.org/wiki/Single-precision_floating-point_format
did you ever work with them in school? having to deal with a exponent/fraction is much more painful than just shifting/dropping bits.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
