Parallel termination resistor on the Rx end

[shaiko]

Many times I see designs that use a 50 Ohm parallel termination on the Rx end of a FPGA Tx buffer.
How is this possible?
If we calculate the current for LVCMOS 3.3 - it will be:
3.3/50 = 66mA

Can the output of an FPGA drive such a high current ?

 

[FvM]

Typical maximum continuous output current ratings are 20 to 40 mA, depending on the FPGA family.

It's unlikely that the circuit uses a static termination to GND or VCC for a 3.3V IO standard. You should look more thoroughly at the circuit. There are possible options like dynamic termination, termination to reference voltage (SSTL IO standards used for DDR RAM).

 

[shaiko]

What is a dynamic termination ?

 

[FvM]

RC series termination.

 

[shaiko]

what is the purpose of such a termination ?

 

[gbounce]

power dissipation at DC is one

in space applications series source termination is generally preferred to save on power consumption, compared to say parallel termination

 

[shaiko]

I know about the advantages of series terminaton over parallel.

However,
In my application, the Rx end - is always active while the Tx end is sometimes switched off (High 'Z').
This way, the parallel termination will come with the benefit of setting a known electrical level at the Rx end (when the Tx is switched off).

The problem is that the transmitter cannot drive such a high current.
Any suggestions?

 

[FvM]

50 ohm load side termination is usual for IO standards like ECL/PECL and SSTL. These standards have reduced voltage swing and a dedicated termination reference voltage, so the output current and static power dissipation is considerably reduced.

You didn't yet clarify which IO standards your initial question refers to.

Setting a known level for an undriven line doesn't require a low impedance termination. Weak pull-down or pull-up resistors are usually sufficient.

50 ohm load side termination is rarely used for IO standards with large voltage swing, e.g. 3.3V LVCMOS. If it's intended for some reason, drivers with larger output current capability are required.

I agree about source side series termination as the preferred termination method for most cases. It's also a kind of dynamic termination, because it only absorbs reflected waves at the signal edges but doesn't cause static power dissipation. Using a RC series termination at the load side can be a solution in some cases, e.g. for nets with branches, but it's more a compromise, not so straigthforward as source side series termination.

 

[shaiko]

The standart I'm using is 3.3V LVCMOS.

Setting a known level for an undriven line doesn't require a low impedance termination.

I know that...the reason I thought about 50 Ohm is because I wanted it to be dual purpose:

1. Match the transmission line's impedance when the Tx buffer is active.
2. Pull down the logic level to '0' when the Tx buffer is high 'Z'.

This would seem as the ideal solution to me if my Tx buffer could drive high current - which it can't.
Any idea for a solution to achieve both of the above goals?

 

[gbounce]

in a lot of cases you can have something like this:

fpga output -> series resistor -> output driver ic -> series resistor -> receiver ic -> series resistor -> device, or whatever termination you want

you let the driver/receiver chips do all the heavy lifting and define the signaling standard (rs422, lvds, whatever)

 

[FvM]

I would use a combination of source side series termination and a pull-down resistor (e.g. 1 k) for LVCMOS. The most serious limitation of source side termination should be however considered: It achieves an optimal waveform only at the far (load) end of the transmission line.

But. Having a tristate driver driving the net suggests that there are more than on driver. In this case, neither simple source nor load termination is sufficient, depending on the net topology.

 

[shaiko]

But. Having a tristate driver driving the net suggests that there are more than on driver. In this case, neither simple source nor load termination is sufficient, depending on the net topology.

No. The Tx is the only driver. It is however turned off most of the time (to save power).
You suggest a series termination of around 1K together with a 50 Ohm parallel resistor at the Rx side. I thought about that - but signal integrity simulations suggests that the signal will look "unpretty" with such a solution...

 

[K-J]

No. The Tx is the only driver. It is however turned off most of the time (to save power).
You suggest a series termination of around 1K together with a 50 Ohm parallel resistor at the Rx side. I thought about that - but signal integrity simulations suggests that the signal will look "unpretty" with such a solution...

There's also the practical aspect which in this case is that almost any termination will be far better than no termination. Change the 50 ohm to 100 or 120 ohm and the DC load will drop significantly and the impact on signal integrity will be minor. Run the sims and check on the scope and you'll see for yourself.

Kevin Jennings

 

[RCinFLA]

At receiver end have a 100 ohm to 3.3v and 100 ohm to ground. Load current will be about 33 mA which should be driveable by FPGA. If you want to help things further the FPGA driver will likely have greater pull down then pull up current capability. You can put a little less then 100 ohms to 3.3 v supply and and a little greater then 100 to ground. Parallel combination of two keeping to 50 ohms.

If you need low power idle then have to switch off the 3.3v supply to resistor.

 

[BlackHelicopter]

RC series termination.

I've seen this a lot and never really understood it, more specifically how the R and C values are determined.

 

[FvM]

No. The Tx is the only driver. It is however turned off most of the time (to save power).

A static driver with series termination won't consume power as well. I dosn't see a reason to tristate the driver.

I've seen this a lot and never really understood it, more specifically how the R and C values are determined.

For a "Rx" termination e.g. R = ZL, RC > TD (transmission line delay).

 

[shaiko]

K-J ,
parallel 120 Ohm is also too much.
You see the driver isn't an FPGA buffer, it's a clock oscillator that can push 7mA at best.

FvM,
To save power, the clock's Vcc itself is cuttoff - so the output is floating.

 

[FvM]

To save power, the clock's Vcc itself is cuttoff - so the output is floating.

The output will be floating if the I/O supply voltage is turned off. Most FPGA families are not designed to allow selective power supply deactivitaion, by the way. Anyway, a pull-down resistor with large resistance compared to the trace impedance will be sufficient to set a defined level for the signal. The termination options have been discussed. I didn't hear yet any application details that suggest a low impedance "RX" termination.

As an additional point, you'll usually have both side terminations for signals with > several 100 MHz data rate or longer traces. But neither of these cases would use a high voltage swing IO standard like LVCMOS.

 

[shaiko]

The output will be floating if the I/O supply voltage is turned off. Most FPGA families are not designed to allow selective power supply deactivitaion.

Sorry if I wasn't clear enough - as I mentioned before, the Tx buffer is a clock oscillator and not another FPGA. Sometimes this oscillator's Vcc voltage is cuttoff - It's a given fact for me...

I wanted to use a termination scheme that will give good signal integrity when the clock is turned on and set the voltage to a constant known level when the clock oscillator is high 'Z'

Would you recommand a parallel RC termination for my application ?

 

[FvM]

Good signal integrity with clock turned off spells noise immunity. You need to avoid false clock edges during high 'Z' driver state. Normally the previously suggested 1 k resistor should be sufficient for this purpose. It can be located anywhere in the net. Once again, I would use a series terminated driver and no source side termination. It gives lowest power dissipation and good signal quality.

You have been originally asking for FPGA output drive strenth. The maximum output current of the clock generator may be higher, possibly tolerating 50 ohm termination. But it would be mainly a waste of power.