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Use a level shifter from 5v to 2.75 volt interface. Resistor divide will take high current and it will impact speed also. See if RX device can tolerate 5V input signals. ARe these CMOS chips. Look at maximum ratings also.
For supplying 2.75 resistor divider is not right as it has to drive power...
From all circuits, Current I1 will increase due to power supply change. As trasistor M43 is single transistor and node 18 will change with power supply. If you can try using a cascode for this transistor, then impact of power supply on I1 will be minimum. I2 looks perfect. Then "I2-I1" i.e...
There can be multiple reasons for this. First the bias current itself will change due to finite output impedance of the current source. Then gm of input devices will change due to body effect. Can you post your archiecture.
spectre phase noise
Run PSS and Pnoise analysis.
PSS is periodic staedy state. It calculates VCO operating frequency in steady state and Pnoise calculate the phase noise for the defined frequency range.
Increasing delay in reset path is the way to avoid dead zone. Probably you need to check the way you are simulating PFD+Charge pump. You should look into the total charge delivered at the output of charge pump not the current output. Current output will not look very clean and it will give...
Re: VCO noise and divider
You can view it like this. Jitter is remaining same. As no noise is added and time period is doubled. So Phase noise is half. As same jitter for bigger period will translate to smaller noise
Apply input voltage difference between true and complement of +1V and apply 3V at output. Then measure current sink inside the circuit. This will give IOH
Similarly apply negative input voltage and supply a 6mA current to the output pin, and measure the voltage on output node. This will give...
Re: Opamp biasing
Resistor divider will have a higher output impedance. This circuit will have a low output impedance so it will be able to respond faster to changes in output of power amplifier (as this node will be coupled to output). So any changes in utput will affect this bias node also.
Re: bias question
Vnb will be very sensitive to voltage variation on the source side of current mirror. Any difference in the source of current mirror between the 2 will give high mismatch for the current due to devices being in sub-threshold.
Re: Bandgap Opamp
Lower bandwidth will help in reducing the device noise but increase your startup time.
Lower bandwidth will also degrade PSRR at higher frequencies. At around 3bB of opamp PSRR will start degrading. So higher bandwidth will push this degradation to higher frequencies.
It does not say that reference input voltage is higher. It says that input referred noise voltage is higher in 11b.
As in 11a current source drain is common to both differential inputs so noise will be same for both input transistors. So effectively no noise for the differential circuit.
But in...
Startup time is the main issue. Then lot of nodes become really high impedance and gets coupled to power/ground noise. This makes BG outputs to completely die. So need to take care of couplings. Then area is bigger for low power bandgap due to large resistors required for this.
Re: About PLL vco gain
Differential architecture for PLL will help in reducing VCO gain by 2. In this control voltage will be differential, so for same power rail and same frequency range, control voltage will chnage will be double.
Other way is to have delay cell which changes by small amount...
Startup circuit will work:
Initially R3 will pull down gate of M6 so M6 is off. So Gate of M5 will high turning on M5. This will pull down gate of M1,M2 ,M3 so all current sources starts flowing current so bandgap will start. Once Vref will come up and circuit is self sustaining.
M6 is On which...
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