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Recent content by FPGAs

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    how to realize a SPI interface with VHDL?

    vhdl for spi SPI3 is a simple one. But SPI4.2 is so complexed and difficult
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    What's the difference between CPLD and FPGA design?

    Re: Difference between CPLDs, with their PAL-derived, easy-to-understand AND-OR structure, offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Once programmed, the design can be locked and thus made secure. Most CPLD architectures are very similar, so it is...
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    Does the FPGA will replace ASIC?

    FPGA can't replace ASIC. Because FPGA is also an kind of ASIC.
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    which one is the best eda tool for electronics chip design..

    Re: which one is the best eda tool for electronics chip desi Mentor 's sieries products Synopsys is also OK
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    Who is Market Leader in FPGA - ALTERA or XILINX

    Xilinx. This is a vote results from opencores.org Which FPGA you prefer? (Votes by year) 740 votes in year 2001 Altera 39.7% Xilinx 57.4% Other 2.8% 761 votes in year 2004 Altera 36.5% Xilinx 60.0% Other 3.4% 834 votes in year...
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    Help me write test codes for shift register

    Re: shift register The above testbench code can only be simulated in Modelsim enviroment. In real world, for example your U2P board, you have 2 choice. One is use sierial data and clock generator(PCM etc.). Another is generating data and clock by your CLPD itself. cnt8 : a counter of 8 temp...
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    Setup n Hold Voilation in timing report

    For synchronous circuits, it's OK if there is no timing error. But, for asynchronous circuits, no timing error doesn't mean it meet design specification.
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    VHDL/FPGA Simulation + PROTEUS (!)

    fpga proteus Modelsim can do that! VHDL can support TCL scripts. You can creat a CPU module using VHDL, and type TCL command in modelsim.
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    [SOLVED] differences between amplify synplify and XST

    As far as synthesis efficency, synplify is better than XST. But for some xilinx's embedded IP core, XST is OK.
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    Anyone can tell me how to simulate a digital PLL with matlab

    digital pll matlab and then implement this PLL using VHDL in FPGA design？ I am very intrested in it. Thanks advance!! Added after 25 minutes: sorry. add another question. Which book is OK when start FPGA design using matlab?
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    Help me write test codes for shift register

    Re: shift register I write a simple testbench, and you can write a more comprehensive testbench. entity tb_shift_register4 is end entity tb_shift_register4; architecture behav of tb_shift_register4 is signal reset: std_logic:='1'; signal clk : std_logic:='0'; signal si ...
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    Warning: NUMERIC_STD.TO_INTEGER: metavalue detected

    numeric_std.to_integer: metavalue detected aji_vlsi, Thanks for your answers. "These messages can be turned off by setting the NumericStdNoWarnings variable to 1 from the command line or in the modelsim.ini file." How to turn off the NumericStdNoWarnings in modelsim.ini file? And this is...
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    fpga based network projects

    Please tell us more details. Which kind of network?
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    Warning: NUMERIC_STD.TO_INTEGER: metavalue detected

    explain to_integer function Thanks to nand_gates. I read a memo in Modelsim help, which is "These messages can be turned off by setting the NumericStdNoWarnings variable to 1 from the command line or in the modelsim.ini file." I turn off it in modelsim.ini file, but it don't affect, why?
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    Warning: NUMERIC_STD.TO_INTEGER: metavalue detected

    metavalue detected Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 My modelsim report it, why? How can i solve it? plese help me with some idea, thanks a lot!
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