Setup n Hold Voilation in timing report

[nic4u]

guide to understand setup timing report

can anybody tell me by reading timing report , how do we exactly come to know if there is
1) setup voilation
2) hold voilation

m asking specifically for Xilinx ISE

thnx in advance

 

[nic4u]

m dissapointed with no answers

ok....then plz tell me this:

For Xilinx ISE, in the twr(timing report) file, at last there is always a table tht shows some setup and hold values...some positive ...some negative n some zero(for hold)....plz help me decode this table....wat do these positive n negative values signify....

hope to get an answer soon frm some expert

or at least tell me if there is any documentation on various reports generated by Xilinx ISE tool....

thnx

 

[echo47]

The "TRACE" chapter of the ISE "Development System Reference Guide" describes the Trace Report (timing report).

This is basically how I deal with timing:

First I add timing constraints to my design. Very important!

Then I synthesize it, route it, and run Trace (the timing analyzer). If the timing report shows zero timing errors and "all constraints were met", then the design is good to go, with no setup or hold violations or other timing problems. If Trace detects some problems, then the timing report gives details about the worst offenders. Of course, to get an accurate report, I must use comprehensive timing constraints.

 

[FPGAs]

For synchronous circuits, it's OK if there is no timing error.
But, for asynchronous circuits, no timing error doesn't mean it meet design specification.

 

[echo47]

ISE provides timing constrains for asynchronous circuits too. The timing report will show non-compliant signals.

 

[nic4u]

thnx echo..tht was of gr8 help

can u tell me why dont we get Hold violations in FPGA(plz correct me if i m wrong)

i think, setup voilations are checked n reported directly through the Input Offset Constraint(if it's met then no violations...correct??).....but i've never seen any hold voilation in any of my designs....

the Trace tutorial says if hold violations r there, it will report u....did anybody ever get Hold violations...if yes can u plz share tht...(if possible plz share ur timing report also..tht will b of gr8 help)

thnx

 

[echo47]

I have not encountered any hold violations in ISE, but apparently they do occur in certain situations.
Search the Xilinx web site for "hold violation", and you'll find some examples.

Yes, setup and hold timing is checked at the pad input flops, and everywhere else inside the FPGA, if you specify appropriate timing constraints.

Input Offset constraint -- I haven't used that one for a long time, so I'm not sure about its behavior.

Xilinx constraint syntax can be confusing. It's easy to specify constraints that don't do what you intended them to do.