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fmaximovic

Recent content by fmaximovic

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UNDEBUGGABLE X values in simple module

I also posted the schematic and the constraint file; if the problem is not in the structure, the testbench, the code, the constraint file... what else could it be?
- fmaximovic
- Post #3
- Oct 8, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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UNDEBUGGABLE X values in simple module

In my very simple schematic A there's something I'm not able to fix; its behavioral simulation had no problems but the timing one is a disaster (cf B, zoomed in C). The first block performs the sum INTER_1 of two inputs A1 and A2; then INTER_1 is fed to a second block that sums (subtracts it)...
- fmaximovic
- Thread
- Oct 7, 2012
- Replies: 3
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Timing constraints: Offset In and Offset Out

Hello, I'm working on a VHDL project using Xilinx ISE 14.1 and I'm facing some trouble with Timing Constraints. As far as the Period constraint is asked there's no problem, I understand it; what's bugging me is how to choose the offset in and out constraints: I've never done it before and I...
- fmaximovic
- Thread
- Oct 2, 2012
- Replies: 1
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Different delay in Behavioral and Timing Simulation

Sure. Actually the block performs a sum between two inputs. Here are its ports clk: in std_logic; reset: in std_logic; en: in std_logic; -- enable A1 : in std_logic_vector(7 downto 0); A2 : in std_logic_vector(7 downto 0); SUM12 : out std_logic_vector(8 downto 0)...
- fmaximovic
- Post #3
- Sep 28, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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isim simulation.........how to use effectively..........

lol... educational
- fmaximovic
- Post #5
- Sep 28, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Timing Simulation: X values even with SLOW clock

Not really, the only varying inputs are 2, i.e. clock and data input...
- fmaximovic
- Post #8
- Sep 28, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Different delay in Behavioral and Timing Simulation

Hi all, suppose that I have a block whose task is adding 1 to its input and output the result after 1 clock delay; also suppose that the behavioral simulation worked just fine. If the post-PAR (timing simulation) shows a different result, i.e. that the result comes out after 2 clock delays...
- fmaximovic
- Thread
- Sep 28, 2012
- Replies: 4
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Timing Simulation: X values even with SLOW clock

subs_1 is the output of the adder (actually subtractor) fed to the block outputting "X"; it's lamba_1 - lambda_2; sq is the signal I've been talking about (the one outputting "X", the one named SUB12 in the code given in the first post - - - Updated - - - sorry, I just corrected my post (this...
- fmaximovic
- Post #6
- Sep 27, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Timing Simulation: X values even with SLOW clock

Well, En is always, always high. A2 comes from an upstream module which is basically and adder, I'm posting more details below. Right. The testbench isn't too big: I have 2 inputs (Lambda_1 and Lambda_2) synchronous with the clock; a module sums them and outputs a signal (Subs_1) which is fed...
- fmaximovic
- Post #4
- Sep 27, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Timing Simulation: X values even with SLOW clock

Hi all, one of my VHDL modules produces "X" values even with the slowest clock; there were no problems with its behavioral simulation though. Here's the code; basically it's an adder (it sums its single data input A2 to a constant FO1 after reshaping A2 into the variable A1) whose output is...
- fmaximovic
- Thread
- Sep 26, 2012
- Replies: 7
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Feedback loops in synchronous processes - VHDL schematics

That's what I did, as anticipated; apparently it's working. Thank you. Thank you all guys for answering, it helped.
- fmaximovic
- Post #10
- Sep 18, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Feedback loops in synchronous processes - VHDL schematics

I will. Actually, maybe I am already : the "adder" has two inputs besides the clock; the output is fed back as one of the inputs without being delayed. Is this what you suggest?
- fmaximovic
- Post #7
- Sep 17, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Feedback loops in synchronous processes - VHDL schematics

and there is no need to delay the input I feed back to it, right?
- fmaximovic
- Post #5
- Sep 17, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] Feedback loops in synchronous processes - VHDL schematics

let's say i have to compute a+b, where b is the output of the block that performs the sum. my point is: if the adder has 3 ports (a,b, clock), can I just feed b back as input without a one-clock delay? or do I need a register that holds for one clock cycle the output of the adder before feeding...
- fmaximovic
- Post #3
- Sep 17, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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[SOLVED] VHDL incomplete if statements in clocked processes

thanks trickydicky, that's what i was searching
- fmaximovic
- Post #3
- Sep 17, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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fmaximovic

Welcome to EDAboard.com

Recent content by fmaximovic

UNDEBUGGABLE X values in simple module

UNDEBUGGABLE X values in simple module

Timing constraints: Offset In and Offset Out

Different delay in Behavioral and Timing Simulation

isim simulation.........how to use effectively..........

Timing Simulation: X values even with SLOW clock

Different delay in Behavioral and Timing Simulation

Timing Simulation: X values even with SLOW clock

Timing Simulation: X values even with SLOW clock

Timing Simulation: X values even with SLOW clock

[SOLVED] Feedback loops in synchronous processes - VHDL schematics

[SOLVED] Feedback loops in synchronous processes - VHDL schematics

[SOLVED] Feedback loops in synchronous processes - VHDL schematics

[SOLVED] Feedback loops in synchronous processes - VHDL schematics

[SOLVED] VHDL incomplete if statements in clocked processes

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