Timing Simulation: X values even with SLOW clock

[fmaximovic]

Hi all,

one of my VHDL modules produces "X" values even with the slowest clock; there were no problems with its behavioral simulation though.
Here's the code; basically it's an adder (it sums its single data input A2 to a constant FO1 after reshaping A2 into the variable A1) whose output is forced to 0 if the result is negative

entity FUE is
port(
    CLK    : in std_logic;
    RESET  : in std_logic;
    EN     : in std_logic; -- enable
    A2     : in  std_logic_vector(8 downto 0);
    SUB12  : out std_logic_vector(7 downto 0)
    );
end FUE;


architecture BEHAVIORAL of FUE is
    constant FO1: std_logic_vector (7 downto 0):= "00001010";
begin
    AWS_P : process (CLK,RESET)
        variable A1      : std_logic_vector(7 downto 0);
        variable AWS_TMP : std_logic_vector(7 downto 0);
	variable CONT0   : std_logic;
    begin
        if RESET='1' then
	    SUB12<=(others=>'0');
        elsif (CLK'event and CLK='1') then
            if EN='1' then
		A1:=A2(8) & A2(8 downto 2);
		if (A1(7) ='0') then
		    AWS_TMP := conv_std_logic_vector(conv_integer(FO1) - conv_integer(A1),8);
		else
		    AWS_TMP := conv_std_logic_vector(conv_integer(FO1) + conv_integer(A1),8);
		end if;-
		CONT0:=AWS_TMP(7); ------------------------ from here
		if (CONT0='1') then
		    SUB12 <= "00000000";
		else
		    SUB12 <= AWS_TMP(7 downto 0); 
		end if;----------------------------------------- to here
            end if;
	end if;
    end process;
end BEHAVIORAL;

Interestingly enough, if I comment the section between "---- from here" and "---- to here" in the above code, no X values result in the timing simulation.

Any suggestions?

Thank you!


PS: My UCF file is made up by the following line

NET "CLK" PERIOD = 4 ns HIGH 50%;

 

[permute]

either En or A2 is not correct.

 

[TrickyDicky]

you havent posted the testbench or the output waveform.

 

[fmaximovic]

either En or A2 is not correct.

Well, En is always, always high. A2 comes from an upstream module which is basically and adder, I'm posting more details below.

you havent posted the testbench or the output waveform.

Right. The testbench isn't too big: I have 2 inputs (Lambda_1 and Lambda_2) synchronous with the clock; a module sums them and outputs a signal (Subs_1) which is fed to the module producing the "X" values.

Here are some excerpts from the testbench.

SIGNAL LAMBDA_1	:	STD_LOGIC_VECTOR (7 DOWNTO 0):="10000001";
SIGNAL LAMBDA_1	:	STD_LOGIC_VECTOR (7 DOWNTO 0):="10000001";


constant mxp1		: std_logic_vector (7 downto 0):="01111111"; -- maximum positive value
constant mxn1		: std_logic_vector (7 downto 0):="10000001"; -- minimum negative value
constant un1		: std_logic_vector (7 downto 0):="00000001"; -- unitary term used in sums


tb : PROCESS(clk)								
BEGIN
      if (clk'event and clk='1') then
		if LAMBDA_2=mxp1 then
			LAMBDA_1<=LAMBDA_1+un1;
			LAMBDA_2<=mxn1;
		else
			LAMBDA_2<=LAMBDA_2+un1;
		end if;
	end if;
END PROCESS;

The output waveform did not help me because "X" comes out without a particular pattern of the input signal:

 

[TrickyDicky]

Its not clear what the signal sq is - its not in either bit of code.

 

[fmaximovic]

subs_1 is the output of the adder (actually subtractor) fed to the block outputting "X"; it's lamba_1 - lambda_2;

sq is the signal I've been talking about (the one outputting "X", the one named SUB12 in the code given in the first post

- - - Updated - - -

sorry, I just corrected my post (this one)

 

[TrickyDicky]

X is usualy a problem of two things driving the same signal. Is sq being driven from anwehere else?

 

[fmaximovic]

X is usualy a problem of two things driving the same signal. Is sq being driven from anwehere else?

Not really, the only varying inputs are 2, i.e. clock and data input...