UNDEBUGGABLE X values in simple module

[fmaximovic]

In my very simple schematic A there's something I'm not able to fix; its behavioral simulation had no problems but the timing one is a disaster (cf B, zoomed in C).

The first block performs the sum INTER_1 of two inputs A1 and A2; then INTER_1 is fed to a second block that sums (subtracts it) to a constant.

The code is after the jump.



Code of the first block (sums two 8-bit inputs into a 9-bit output):

process (CLK)
   begin
		if (CLK'event and CLK='1') then
			S1 <= conv_std_logic_vector(conv_integer(A1) + conv_integer(A2),9);
		end if;
   end process;

Code of the second block:

architecture BEHAVIORAL of FUN_21 is
    constant FO1		: std_logic_vector(7 downto 0):= "00001010";
begin
   process (CLK)
		variable RES_TMP 	: std_logic_vector(7 downto 0);
   begin
		if (CLK'event and CLK='1') then
			if (B1(7) ='0') then --V1
				RES_TMP := conv_std_logic_vector(conv_integer(FO1) - conv_integer(b1),8); --V1
			else
				RES_TMP := conv_std_logic_vector(conv_integer(FO1) + conv_integer(b1),8); --V1
			end if;
				T1 <= RES_TMP(7 downto 0); 
		end if;
	end process;
end BEHAVIORAL;

UCF file:

NET "CLKX" TNM_NET = "TMN_CLKX";
TIMESPEC "TS_CLKX" = PERIOD "TMN_CLKX" 4 NS HIGH 50%;

And the testbench code is:

CLKX <=not CLKX after 2 ns;

   process(CLKX)
		constant MXP1		: std_logic_vector (7 downto 0) := "01111111"; -- maximum positive value
		constant MXN1		: std_logic_vector (7 downto 0) := "10000001"; -- minimum negative value
		constant UN1		: std_logic_vector (7 downto 0) := "00000001"; -- unitary term for sums
   begin
      if (CLKX'event and CLKX='1') then
			if IN_2 = MXP1 then            -- if IN_2 reached its positive maximum, reset it
				IN_1 <= IN_1+UN1;		  -- and increase by 1 IN_1
				IN_2 <= MXN1;
			else
				IN_2<=IN_2+UN1;			  -- else increase IN_2 by 1
			end if;
		end if;
   end process;

Ah, and of course the Timing Report said that there were no violations.

Thank you all guys!

 

[std_match]

The problem is not in the code you posted.

 

[fmaximovic]

The problem is not in the code you posted.

I also posted the schematic and the constraint file; if the problem is not in the structure, the testbench, the code, the constraint file... what else could it be?

 

[barry]

A few points:

Your code references "CLK", but your constraint is on "CLKX". Is CLK defined as CLKX somewhere? If not, then it looks like there's no constraint on CLK
Maybe you should try getting rid of those conversion functions and see if it works. It's not clear why you are converting std_logic_vectors to integers and then converting back again. Maybe you should be using signed or unsigned types, and the std_numeric library.