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Recent content by FixitFast

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    does the following two codes in VHDL mean same. What is difference in implementaion

    Hello every one. The two codes are below if(valid_shift_HIGH = '1') then if(buff_2Sn_empty = '0' and buff_2Sn_1_empty = '0') then rden_buff2 <= '1'; else rden_buff2 <= '0'; end if; else rden_buff2 <= '0'; end if; the other is rden_buff2 <= valid_shift_HIGH and (not...
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    code for cross clock domain DATA

    Helloo every one I need to ask about the following code if it works fine in the practical two cross clock domain systems. in simulation it works but I have reservations since this method looks fine for 1-bit signals, but for a data bus I am not sure hence want to ask module clk_2_cross (...
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    signal between two clock domains. (code verification)

    Yes you are right, later I realize this thing when I see deeply... what to do then...Is this thing (simple 2 FF synchronizer for removing metastability) all right
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    signal between two clock domains. (code verification)

    hi all I have one signal that works in a module where there are 2 clocks of different frequencies. Actually I had and have been using the code for single pulse if it is between two clock domains, but now this signal is not a pulse, but a signal that remains HIGH for longer period of time (shows...
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    what happens to the timing statements during synthesis

    Thanks for reply. so you mean to say that after stipping of the timings (i.e. non-synthesizable part) the rest of the thing will be transformed into form of gates or will they be ignored completely. I mean it is not like using, synthesis on - synthesis off statement, right! I emphasis more...
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    what happens to the timing statements during synthesis

    hi all my question is based on following code snippet that I have seen on the 3rd party development kit I am using ... ... case reset_state_r is ... ... when RESET_DISABLE_CLK => en_clk_off_cnt_r <= (en_clk_off_cnt_r + '1') after (100)*1 ps; if...
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    what is the reason for data mask pin in DDR3

    Hi all what is the reason of data mask pin in DDR3. What if I make it disable? please reply
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    job opportunities in FPGA design fields

    Hi all, I am about to enter in the field of job market and I am very enthusiast about joining in the field of VLSI. I have done 1 or 2 small projects and 1 freelance project of medium size. but moreover I really find this field interesting and I would say I am of course not very good not. but I...
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    process statement, How much it can handle

    Hi all, First of all, Does One sequential PROCESS statement means 1- Clock global line ? I have seen in some code that inside one process statement they have several IFs-else and etc. Apparently they should run in Parallel, since they are merely making a Logic element, but by the definition of...
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    how to I find (approximately, not precisly) the delay in if statement

    Well... This is possible... What I only changed is the OFFSET IN for input pads and OFFSET-OUT for output pads to 20% of the clock cycle. i.e. 4ns * 20% = 0.8 ns And now the best achievable case is 3.956 ns. I did not change anything in the code. I guess the Routes that FPGA follow changes as...
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    how to I find (approximately, not precisly) the delay in if statement

    Thank you for your reply. Can you just verify that by logic levels you mean the # of combinational blocks b/w two end points ! Also I made a run of my design and got 12 errors for timing analysis... I have confusion over what OFFSET IN and OFFSET OUT value should I put in. When I was doing, I...
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    how to I find (approximately, not precisly) the delay in if statement

    Thank you for your replies Since the combinational logics add up to make the critical path, hence I was asking this. In actual I am not concerned about the combinational delay, but the dela path b/w register to register, if you may say... I am asking about delays because I am concern about if...
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    how to I find (approximately, not precisly) the delay in if statement

    Please consider the following condition (Language is VHDL) Now in Xilinx, virtex-6 what is the general gate delay for AND/OR NOT etc. ( or any general Xilinx FPGA) It is because I am not an expert programmer and hence my logic includes this type of IFs, hence I need to know the timing since I...
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    [SOLVED] Critical timing or circuit deisgn timing increased or affected. How and why?

    That is exactly what I mean... By better coding design you mean 1. as less nested IFs as possible 2. pipelinings. ( I find it hard part, frankly) 3. avoid combinational ckts. 4. and...?
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    [SOLVED] Critical timing or circuit deisgn timing increased or affected. How and why?

    Hello, I also have a similar question. (sorry for I am not capturing the post). 1. While programming in HDL(VHDL/Verilog), how can we take care of the maximum frequency. and will the same code for two d/f/ FPGAs create different ckts having f/d clock frequency. For example I have an IP for ADC...
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