how to I find (approximately, not precisly) the delay in if statement

[FixitFast]

Please consider the following condition (Language is VHDL)

if(data_nbr < total_data and data_fetch = "01" and (write_dpath = '1' or wr_start = '1') ) then --and ddr_tx_cmplte = not_complete

Now in Xilinx, virtex-6 what is the general gate delay for AND/OR NOT etc. ( or any general Xilinx FPGA)
It is because I am not an expert programmer and hence my logic includes this type of IFs, hence I need to know the timing since I have timing requirement for my design.
I look at virtex-6 data sheet but could not find the answer

Waiting for answer.

 

[mrflibble]

Simplest way for the non-expert programmer is to synthesize a small test design with your piece of code in it, synthesize it and then 1) see what the synthesized result is 2) see what kind of delays you are getting (in the timing report) and 3) use this information to take a step from non-expert to slightly-less-non-expert.

 

[TrickyDicky]

If you're worrying about delays for combinatorial code in an FPGA, you're either "doing it wrong" (and should be using synchronous logic) or you're a highly advanced engineer doing some crazy stuff (and probably wouldnt be asking here).

Why are you asking about delays? surely you know the max delay acceptable because you know your clock speed?

 

[FixitFast]

Thank you for your replies

If you're worrying about delays for combinatorial code in an FPGA, you're either "doing it wrong" (and should be using synchronous logic) or you're a highly advanced engineer doing some crazy stuff (and probably wouldnt be asking here).

Why are you asking about delays? surely you know the max delay acceptable because you know your clock speed?

Since the combinational logics add up to make the critical path, hence I was asking this. In actual I am not concerned about the combinational delay, but the dela path b/w register to register, if you may say...

I am asking about delays because I am concern about if in the final of the code I am stuck with the clock speed not able to match my design clock (around 250 MHz)

see what kind of delays you are getting (in the timing report)

By this you means the (in ISE) ' Analyze Post-place and Routing Static Timing ', right? under Place&Route -> Generate post-place & static Timing

 

[TrickyDicky]

then you need to look at the timing reports. If it fails, then you need to repipeline.
At 250Mhz, you should be fine with a couple of levels of logic. Its difficult to tell what exactly your code will map to as the synthesisor may make several logic optimisations. So the only way to tell is compile it.

 

[mrflibble]

By this you means the (in ISE) ' Analyze Post-place and Routing Static Timing ', right? under Place&Route -> Generate post-place & static Timing

Yup. And in general 250 MHz should be no problem on a virtex-6, as long as you don't have an insane number of logic levels.

 

[FixitFast]

Thank you for your reply.

Can you just verify that by logic levels you mean the # of combinational blocks b/w two end points !
Also I made a run of my design and got 12 errors for timing analysis...

I have confusion over what OFFSET IN and OFFSET OUT value should I put in. When I was doing, I just run with the default values, i.e. 4ns for clock and similary OFFSET IN AND OUT also 4ns...Although I have concept of offset in and offset out theory, but what timing values ( I think it depends on percentage of clock cycle, right?) I should put in, I don't actually know.

Also is offset in = setup time and offset out = hold-time
Note that I have not assigned the pin connections now(since it is the sub block that I analyzed). Only the timings.

Please see the picture below.

 

[TrickyDicky]

I dont know about offset in and out - Im not really a timing specs guy. But by levels of logic I mean

registers -> logic element 1 -> logic element 2 -> register.

LE1 could contain several gates, depending on the family of devices you're using. a 6 input LUT can have many more gates in it than a 4 input. So that "if" statement you have may fit in a different number of LEs depending on family. This rule of thumb also breaks down when the chip starts getting full (say > 70% ) as routing can cause more issues than the actual LEs when it decides to put the two LEs at other ends of the chip.

 

[FixitFast]

Well...

This is possible... What I only changed is the OFFSET IN for input pads and OFFSET-OUT for output pads to 20% of the clock cycle. i.e. 4ns * 20% = 0.8 ns

And now the best achievable case is 3.956 ns. I did not change anything in the code. I guess the Routes that FPGA follow changes as I changed the timing parameters.
Now having no timing constraint violation.

Thanks

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I dont know about offset in and out - Im not really a timing specs guy. But by levels of logic I mean

registers -> logic element 1 -> logic element 2 -> register.

LE1 could contain several gates, depending on the family of devices you're using. a 6 input LUT can have many more gates in it than a 4 input. So that "if" statement you have may fit in a different number of LEs depending on family. This rule of thumb also breaks down when the chip starts getting full (say > 70% ) as routing can cause more issues than the actual LEs when it decides to put the two LEs at other ends of the chip.

wow! I never knew we have to keep these things in mind while coding....!

btw I got my previous post answer in your last sentence.

Thanks

- - - Updated - - -

pardon me can I ask what you mean by

Im not really a timing specs guy

since as I see in Xilinx ISE, it just take a little amount of time and effort to set timing parameters...
Is it quite a different thing for large projects?

 

[TrickyDicky]

It can really depend. My background is algorithm implementation, and only recently was handed a project where my job is to make the design meet timing. The project file is 3600 lines, which about half are logic lock regions and specs (to help timing at the fit stage - ie. group related logic together and not spread it all over the place) and the timing SDC file is 900 lines. Logic = 70%, DSPs at 80% and memory at 90%. This is a large Stratix 4, with one clock at >350MHz

 

[syedshan]

Hi TrickyDicky,

If you do not mind I am interested to ask you about the fields you have just mentioned...

Algorithm Implementation : So this is the field where you have, lets say, any signal processing task to done and you develop algorithm for it and later implement it over the HDLs. Later logic simulation is also your part. But isn't not timing simulations a part of timing analysis ! Is this also your part if you are working only as the algorithm implementation
In this phase usually guys work alone or in a group...since understandding one's code is quite a hectic for others, also the way HSL people code also differs and may cause circuit timing problems since each one has his own coding skills and implementation style.

As the other part: design meet timing part...What is one's major work, doing place and route manually to do the design timing proper or what?

 

[TrickyDicky]

This can really depend what stage of the design you're at. If you already have a board, you know what clocks are available, or if you can generate other clocks with a DCM/PLL. You should usually what the data rate is required, so it's easy to work out what clocks are required as you should already know what busses or interfaces there are (or if you dont, that should be the first stage) and you work backwards from there. Latency should never be an issue, unless you're doing some real time image processing or something.

So you know what the data rate in and out will be, you know what your internal clock is, so now you just build the design. You can work out the latency from RTL simulation. THen you compile it, run the timing analysis, and if it meets timing, put your design straight on the board, without using the slow and laborious timing simulations (unless you're doing ASIC, then it may be important). The only reason you will need timing simulation is if you have some asynchrnous logic somewhere, but you should avoid this at all costs.