Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
charge pump ac analysis
Hi,
I'm designing a charge pump (phang topology) for memories, using a clock of 100kHz. The charge pump is working, but I'm having a difficult to analyze it in terms of stability.
I want to control the output voltage changing the amplitude of the clock signal, so I...
What is the best choice in rail-to-rail input stages, concerning the CMRR in all the range of operation????
Because in the transition region, the CMRR are degraded a lot using complementary differential pairs.
What could be a good topology to overcome this problem?
Thanks a lot!
Filipe
Re: centroid matching
Does anyone know if there is any paper showing, quantitatively, the effects in matching using common centroid?
I'm very curious about this.
Thanks
gsmc deep nwell
In a mixed signal design, and AD converter, I have more than one voltage supply (VDDA, VDDD, GNDA and GNDD)
In the layout extraction (using calibre), there are 2 ports connected togheter, e. g., at the substrate. So, the LVS failed.
What can i do to eliminate this error...
Hi
I'm a begginer in MC anlysis, and I found 3 options to run it: vary process paramenters (lot), where all transistors vary togheter; vary matching parameters (dev), where the transistores doesnt vary togheter, but all they vary; or the both analysis togheter (dev+lot).
But It's very important...
monte carlo mentor 2008
Hi
Does anyone have a basic and practical tutorial to perform monte carlo analysis using mentor graphics tools???? I need to estimate the random offset in an opamp, and any suggestion about it will be very useful to me.
Thanks a lot!!!!
Filipe
Hi,
I'm designing a SC sigma delta modulator (Fs=5MHz) with 5V supply, and I need 2 reference voltages (1.75 and 3.25V) generated into the chip. So, I think that the best way is to build a BGR (such as PTAT, razavi pg 391, fig 11.20) , and with it, generate the other voltages. Is this a good...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.