LVS with 2 ports at the same substrate

[filipecbv]

gsmc deep nwell

In a mixed signal design, and AD converter, I have more than one voltage supply (VDDA, VDDD, GNDA and GNDD)
In the layout extraction (using calibre), there are 2 ports connected togheter, e. g., at the substrate. So, the LVS failed.
What can i do to eliminate this error???
Thanks

Filipe

 

[milkdragon]

I do not know which process you are using. Typically, foundry provides an extra logical layer to seperate different ground on the same substrate. Simply covers the area you want to have seperate ground and you can eliminate LVS error

 

[Old Nick]

I've dseen this before, or at least something similar (it was a couple of years ago)

What I had to do was connect all the grounds together for the purposes of the LVS, then remove the connections afterwards. It was fairly easy on my design, since I only encountered the problem when the pads were added, and I just connected the pads together, then removed the wires afterwards.

 

[pph_cq]

Check your technology file and LVS command file, there should be a layer to seperate different psub.

 

[protonixs]

if u are using TSMC or GSMC technology, u may use psub2 to isolate those power nodes.
on the other hand, u may use second N well if you are using triple well process.

 

[lsfeng]

In a mixed signal design, and AD converter, I have more than one voltage supply (VDDA, VDDD, GNDA and GNDD)
In the layout extraction (using calibre), there are 2 ports connected togheter, e. g., at the substrate. So, the LVS failed.
What can i do to eliminate this error???
Thanks

Filipe

deep n well process is the solution

 

[electronXwork]

There could be an additional logical layer provided by the foundry use for LVS verification only to seperate the psub of different GND (like DVSS, AVSS) if none some use DSNW (Second NWELL) for triple well process.