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Thanks RobG.
It's nice OP when used as voltage double,
but how could i converte it into step down mode?such as 1/2 with GmV modulation for Vout? i can't work out....
---------- Post added at 03:37 ---------- Previous post was at 03:26 ----------
BradtheRad,
i couldn't understand how it go...
Thanks for your replys!
BradtheRad,
Let's simply calculate, as pnp switch "on" in DT, "off" in (1-D)T,then when system is stable, (Iin-Iout)*DT=Iout(1-D)T--->IinD=Iout;
thus max of η=Pout/Pin=Vout*Iout/(Vin*IinD)=Vout/Vin; so just with this kind of SC capacitors ,we may couldn't get η>Vout/Vin...
how to realize 3.3v to 1.2v(only can use DC-DC without inductor)
hi,all
now i need convert 3.3v or 2.5v to 1.2v~1v in cmos0.13um process. if i can't use LDO, only use DC-DC(but without inductor!).how can i do? the ripple need to keep below 50mv.loding up to 30mA .and efficiency > 60~70%...
thanks for reply.
i've try but , still have problem of the parameters :( .
some eda engineers have done it with script of skill ...but i can't find any guideness or reference....
Hi ,all
since i want to transfer our design(schematic) from one fountry to another(both are 0.13um process,but obvious different pdk and models). if done by hand , it's a big job. someone told me use lib manager-->rename reference library. it works , but many parameters transfer worng(eg...
hi,
i'm a newer in pll, papers often told me the pll bandwidth should less than 1/10 of operation frequency. but how can i got the whole pll bandwidth with hspice? we take a basic pll for eg. vin is input ck,vref is feedback ck. and vout is output ck.
what kind of source should i set?since...
hi all.
it's about chgpm op point for pll in 0.13um process. pm49 is in region 1.nm43 in region 3, while other mos all in saturation,only pm35 is 3.3v device.the supply is 1.2v. each path current is set to 20uA. the op point result is shown in image.
it seems pm49 appear small ron, why...
Hi all ,
It's a problem about 3.3v to 1.2v with no extra power consumption internal chip
for simple application, a digital chip of 0.13um only package with 3.3v IO.since incide of chip need 1.2v supply.so what can i do for simple reliable solution?
the only limit is power...
help for special circuit
Hi guys,
it's about my 0.18um chip design, there's a pad to inside mos gate for voltage check.and the voltage is come out from PCB, so the problem is :
this voltage is early than chip supply(1.8/3.3v),and can up to more than 5v when suddenly power on.so...
Hi, JoannesPaulus
All i mentioned here is about S/H stage for pipelined adc. so i just measure data after S/H, diff sin input with diff sin output. it's the same way for one or differential signal(they're all sine signal).
Since it's easy to get high SFDR of S/H(>90db) for differential...
Yes ,you're right about SFDR with INL(nearly 20log(2^b/INL)),and SQNR related to DNL.
i just care about simulation spec result ,not refer to testing after tape out,so we care sfdr rather than INL/DNL.
but my question is, how these paper's SFDR data come from. singal out? or diff out after...
Hi all,
it's about pipeline adc s/h stage .since i use full differencial structure for it that means vin and vip,after sample and hold ,got voutn and voutp.
we all know sfdr is important to adc performance.so i got sfdr of s/h.the question is sfdr value: voutp=58db,voutn=58db(influence by...
hi ankitgarg0312,
1. i have set accurate=1, in hspice manual ,this means autoset runlvl=5,is this poor priority compare with reltol,delmax etc...?if yes ,i'll remve them,since accurate=1 don't set their value.
2.i'm sorry for it ,i didn't use sweep. just similar with your reply,since measure is...
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