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Yeah no kidding. Thanks guys for the sanity check, I bet the problem is wr_en going high initially and stuffing empty data. The debug was made more difficult because even in version 9.2, the default behavioral models just don't act right. You'd think they'd be able to get it accurate after 9...
Hi,
Might be a dumb question, but I'd appreciate a serious answer nonetheless. I built a fifo in coregen (FWFT) of depth 16 and latched 1 word of data to it. I found that I had to read out 00's 15 times before I saw my data word. This seems... wrong. Is it? I was expecting to get my first...
Re: sar adc gilbert promitzer
Umm don't you actually duplicate the original cap network, then add a series cap between the two banks to make the lower bank look like 1/n? Otherwise your scaling of smallest cap to biggest cap could get rather extreme. I don't have a reference handy, but I know...
You don't really want a fixed current over temp, you want a current that keeps your transconductance fixed over temp. That should fix your gain problem. Vt (or d-Vbe) is the right choice for BJT input stage, dVgs is the right choice for MOS input stage. Dick's advice is a good one, although...
It's used to tell the router where it is allowed to draw M2 to cross over that cell. You can add rowcrossers to your standard digital library to help SPR achieve a smaller size... we hope.
The only rule you need to follow is metal to metal spacing for that layer.
tanner tdb file
MOSIS uses scalable CMOS rules and layers, so all their processes look the same to the layout tool.
When you ship your layout, they will convert it to the specific layers used by that process. So to get started you only need to make a very simple layer setup using the...
Undervoltage detector
I agree with leo - any comparator will be fine. For this application I usually use a simple comparator with hysteresis (cross-coupled mirrors).
The bigger problem is that without the bandgap, this circuit will not know if the input voltage is OK or not OK. Chips using...
You should try differential signalling. And on the PLL side, you will need to square up the signal again by using a schmitt trigger - it's considered bad form to clock a flip flop with a slow edge.
But the best case would be to keep the PLL and crystal osc together on the die, because they...
bandgap reference
Hi,
It doesn't seem too bad, but I agree that it could be improved. 75 dB should be enough gain to keep this profile correct from 2v-6v.
Maybe you get an offset current you weren't expecting.
I'd have to see your op amp to be sure, but I am guessing that somewhere (in a...
To drive the second filter resistor with a low impedance. I guess the output to the filter is a charge pump or something that cannot drive a resistor directly.
But personally, I only use the first part of this compensation - pole zero pair with another high pole to kill off the gain at high...
If it's just a label it will should not show up in your GDS data. But it's best to verify that using jobview because I am not clear enough on your tool and situation to guarantee it for you.
Can you specify if you are talking about labels (like wire labelled VIN) or if you have drawn shapes to make letters?
What you really want to do is call the fab and ask for the jobview for your project. Then you can see what is actually on the mask - and anything on the mask will be in the...
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