Can CMOS buffer drive a 27M clk though on-chip 6000um wire?

[luobo]

bufferdrive

On the chip, there is a PLL which requires a 27MHz reference clock. But the crystal oscillator is far away from the PLL in layout (about 6000um). My job is designing an driver buffer near crystal osc and driving the 27M clock to the PLL though 6000um wire.
I can't use inter-buffer among this long wire because the power of digital core is noisy (routing wire passes though digtial core, only core power exists there). I want to put a large buffer on the near end which uses the power of crystal oscillator. Now I plan to use M5 (top metal) to routing the clock by the both side of which I will put M5 ground shielding. And M4 is also used to shield the bottom of clock wire.
Supposed the clock width is 1um, space to M5 shileding is 2um, the total resistance of wire is 6000 / 1 x 0.04 = 240ohm, the exrtacted cap is about 1.35pF. So the RC constant is 324ps
1) I wonder if I can use a CMOS buffer to drive this 6000um wire.
2) I wonder what's the requirement for the reference clock arrived at PLL. The PLL designer only tell me to minimize the jitter due to power/signal coupling. The clock arrived at far end will not have any jitter due to noise coupling because of the good shileding.
3) But the rise/fall time will be not good due to the big RC constant 324ps. Does PLL care this rise/fall time of referce clock? Our PLL ring VCO osc at 1.35GHz, rms jitter is required <5ps
4) And I put a large CMOS buffer to drive this big loading, I find the transient current is about 20mA at the clock switching. Does it matter?

 

[electronrancher]

You should try differential signalling. And on the PLL side, you will need to square up the signal again by using a schmitt trigger - it's considered bad form to clock a flip flop with a slow edge.

But the best case would be to keep the PLL and crystal osc together on the die, because they share signals, and both need a clean supply voltage.