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by bank selection, you mean the register address for the port registers? So far I have been trusting the definition that MikroC uses by default for register addresses.
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Do you think this could be a hardware issue? As the ports are pulled to 1.6 V even when the...
a very simple test:
RA0_bit = 1;
delay_ms(5000);
RA0_bit = 0;
When I look at the RA0 port signal, it acts as described in the firmware.
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Another observation that these two ports are pulled to 1.6 V even when the microcontroller is in RESET.
I am using PIC16F1783 and MikroC IDE. No matter what I set the port settings for RA6 and RA7 in the firmware (input, output, digital, analog, set to 1, set to zero, etc..), these two ports are constantly pulled up to 1.6 V (I am using a 3.3 V supply). This is not the case for other RA0-RA5...
I am trying to create a behavioral model for a feedback amplifier in SystemVerilog and simulate it. I have included the code of the feedback amplifier below, the module calculates the difference of a scaled sense voltage with a predefined value and multiples the difference by a gain.
module...
I am trying to run automatic routing in Layout XL. I am getting a bunch of warnings complaining that some constraints such as minSpacing and minWidth are missing from rulespec virtuospDefaultExtracterSetup and in the end it says:
*WARNING* Insufficient information in the required constraint...
I have a schematic which is basically a bunch of connected standard cells. I plan to create the layout of the schematic, however the routing will be so time consuming if done manually. I am wondering if automatic routing can be done in the Layout XL tool or I need to use the SOC encounter tool ?
I am trying to import and simulate a subcircuit written in SPICE syntax in Spectre. I have created a symbol and edited the CDF file to point to the name of the subcircuit. In design libraries in ADE I have included the text file of the subcircuit. When I try to run Spectre, I get the following...
Are the parameters corresponding to the appropriate bin simply used? What is this interpolation thing about? (the link that you sent me about parameter binning). The reason I ask is that another corporation is doing some HSPICE simulation using the spice model that I am using and they are...
I looked at the model file. I see the properties WMAX,WMIN,LMAX,.... for different nch models, however I do not see any logical statements on how they are used....Maybe I should refer to the agilent link that you send me to see which model is used based on the input parameters (L,W). But it...
In the generated netlist, I just see 'nch' without any numbering......I opened the CDF properties, I cannot see the numbering there either...I have enclosed a screen shot of CDF properties of the nch mosfet.
I am doing some simulations in using Cadence Virtuoso and ADE. I am using TSCM350 nm kit. I need to see what model file is used to nch,pch transistors that I instantiate. In the properties of the transistors I see nothing relating the model. When I looked at the model libraries included in the...
I was trying to come up with the tentative current waveforms inside a receiver dipole in open circuit configuration, but I faced a contradiction...I assume the current needs to be zero at the both ends of each petal...But how can that be possible without keeping the wavelength unchanged?
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