Convergence issue with feedback amplifier described in SystemVerilog in AMS simulator

[dreamyboy_999]

I am trying to create a behavioral model for a feedback amplifier in SystemVerilog and simulate it. I have included the code of the feedback amplifier below, the module calculates the difference of a scaled sense voltage with a predefined value and multiples the difference by a gain.

module LDO_2p2V_ErrorAmp_zz (OUTP, Vsense);

input real Vsense;
output real OUTP;
parameter real VBG_val = 1.201;
parameter real voltage_div_factor = 0.539539087;
real Vsense_div;
parameter real amp_gain = 10;
assign Vsense_div = Vsense * voltage_div_factor;
assign OUTP = (VBG_val - Vsense_div)*amp_gain;

endmodule

At the top level, 'Vsense' and 'OUTP' ports are connected together to form the feedback. A resistive load is connected between 'OUTP' and ground. I use AMS simulator in ADE to simulate the behavior. When amp_gain is something higher than 5 (approximately), the simulation does not converge (the voltage nodes goes so high (1 GV) and simulation stops). More specifically, the error message is:

ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution. In
some of those attempts, a signal exceeded the blowup limit of its
quantity. The last signal that failed is V(dummy_LDO_tb.net04) =
-1.00003 GV, for which the quantity is `V' and the blowup limit is (1
GV). It is possible that the circuit has no DC solution.

Any thoughts?

 

[erikl]

Perhaps somebody could help you, if you'd show or describe your test bench, too.