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I think it is good to put a dummy resistor if its an array of resistor like two diamentional or you can put a well ring because these resistor may produce a high stress region
if you have any matching or noise constraints then use guardring or else you can use substrate contacts wherever possible. Put as maximum as you can in your layout
Re: Multiple MOS layout
Obviously in parallel, drain and source are interchangable.
it seems you are new to IC layout, Not to worry i would suggest you to first go through the basic IC layout books or tutorial and start doing it.........
For NMOS dont see any problem if you connect both the ground to common substrate of 1.2V and 3.3V devices. For PMOS anyway you are connecting both the NWELLs at different potential
For ESD you should go by recommanded structure by foundry itself
In short Common centroid means if you see from the centre of matching geometry all devices should have same environment from all axis, which is commonly use to reduce the effect of linear process gradient or stress induced mismatch
Ya Alan Hasting is very gud book to refer, see on page no...
It doesnt matter if you surround ur NMOS full with guardring and connect to VSS, its the error looking for two PWELL contacts atleast 20um space each other, it means you have to keep PWELL contacts or guardring minimum 20 um in ur case space between each not more than that (obviously it connect...
hey,
As per your floor plan in attachment, we cant comment more abt it unless we see the schematic, it is depends upon the ckt topology you used.
Related to BGR layout, important points are (An extension to pbobde's points)
1. Layout for BJT ratio x:1 is very important (Put single transistor...
I will suggest you to do EM simulation of your layout or parasitic extraction and find out the minimum acceptable value of spacing between two inductor to avoid mutual inductance. Positive or Negative either type of mutual inductance will affect your LNA gain and other parameters
See what other...
Re: find a single via
Thanks erikl, but i need some clarrification, are u talking about to modify DRC rule set file by this method, if it is
Can you guide me, i mean how to include this with proper syntax, i will try it at my end
waiting for your reply
Dipak
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