Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I needed to micrograph my die and tried with Keyence microscope but it couldn't see the layout past dummy metal fills on top five layers. I have seen people showing micrograph of entire die. how do they manage to do that?
Thanks!
From the foundry, I just found there is no way to block STI. Since I didn't account the effect of STI earlier in my simulation , I decide to block the STI instead of redesigning the circuit. But redesigning is the only option now, it seems. Thanks for your suggestions dick_freebird
Hi guys!,
My circuit can't tolerate change in threshold voltage caused by STI. There is a workaround: if I increase source/drain to channel distance then STI doesn't change the threshold voltage but there are other adverse effects due to increased S/D area.
So I am looking for a way to...
I made meaningful connectivity and still it had the same issue. Then I found there was layer that i forgot to draw to make LVS extract the net33tw device. now it is working fine. thanks!
Thanks Dominik!, it helped me solving subc mismatch between layout and schematic.
Hi guys!
When i copy the layout of the triple well mosfet nfet33tw from the pdk (ibm 130nm) as it is and ran lvs on this single device without any modification or connections, the calibre is unable to recognize the device. Am i missing anything here?
Thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
