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i am not able to solve this problem..i tried all options in the simulator options.one of my friend is using the same softwares and same versions...he is not having this problem...can anyone please help me???
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i am not able to solve this problem..i tried all options in the...
haai
i am using xilinx 9.2 for VHDL/Verilog coding.My simulation tool is Modelsim 10.0.I have set the integrated tools option in xilinx as modelsim.For VHDL it is working perfectly.but when i am simulating Verilog model sim shows the error every time.I am not able to understand what it is...can...
i am a beginner in this forum...so please forgive my mistakes.......
initially i declared SIGNAL I:INTEGER;so it was showing the error....after that i converted it into SIGNAL I:INTEGER range 0 to 127...then that error is gone...but now my problem is something else..if i am giving my first...
sorry about that...i am attaching a code with comments below...if i am executing it creates a logical error...it automatically writes data into my 0th location..even if i am giving "0000011" as the address then it writes data in both "0000000" and "0000011" locations....i am not able to find the...
thank you for your help...
i got another problem when using case....the program works perfectly in -ve edge (IF(CLK'EVENT AND CLK='0')THEN) ..if i am changing that into +ve edge (IF(CLK'EVENT AND CLK='1')THEN) then the program behaves like fatal error.an error message is also produced...i am...
what will happen if i am using two if-end if blocks inside a process in vhdl??it will be executed sequntially or parallelly??
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use...
hai
i was writing one code for booth multiplier in vhdl.i am attaching the code below.logically it is correct but I am not getting the output..can anybody help me
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use...
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