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I have seen a datasheet of 12b 100M adc designed by IQ-analog. It only comsume 20mw power in 100MHz. Can anyone give me some information about how to realize the performance?Can anyone give me some materials?Thank you very much.
the datasheet is in the following,
The circuit is used in a high speed sample hold circuit. The output swing for both circuit is enough.
So can any one tell me which one is better, the right or the left? Why?
3X!
Hi,
I meet a problem of convergence when I use veriloga to model the SH circuit.
I first use veriloga to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with spectre, It tell me no convergence, how can I do with this problem?
thx!!
I have a question about DS1302,but I cannot use MCU to solve it, and I hear that there are a lot of people have used DS1302 in this place, so I hope someone can help me here.
If we write a minute signal into DS1302, as we know, the biggest number of minute is 59,then if I write 65 to the...
I want to generate a 10bit digital signal of a sinwave for the pattern generator to test a 10bit DAC. I device I use is Agilent's Logic Analyzer. It need to import a csv file for the test. So can anyone tell me how to generate the csv file?
Thanks a lot.
When I do my ADC simulation with the internal reference, the reference could not fixed, it changes very slow. About 600uV per uS in the simulation.For example, the refn is 1.0V at the first, after 10us' simultion it becomes to about 1.006v,and refp from 2.0 to 1.994, so the refp-refn changes...
It's a current steering DAC, I also do some test when Fs=100MHz, Fin=1M. The result is in the pic.
I'm sorry the pic is large,but you can see it more clearly.
I have a DAC taped out and test. The following is some of the test result. in the first one, the Fs=100MHz Fin=100k and the result is ok. In the second one, the Fs=125MHz Fin=100k and something is wrong with the DAC.
The capture instrument I used must work below 50MHz, so when I did my test, I...
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